Abstract: In recent years, the idea that "Moore's Law" is coming to an end has become popular, and the "post-Moore era" has long become a hot word in the industry. The question that arises is, how to continue to improve the performance of the chip under the existing process process, but also keep the cost unchanged or reduced? In this regard, Chiplet and advanced packaging technology are highly expected by the industry to continue the "economic benefits" of Moore's Law from another dimension.
In recent years, the idea that "Moore's Law" is coming to an end has become popular, and the "post-Moore era" has long become a big buzzword in the industry. The question that arises is, how to continue to improve the performance of the chip under the existing process process, but also keep the cost unchanged or reduced? In this regard, Chiplet and advanced packaging technology are highly expected by the industry to continue the "economic benefits" of Moore's Law from another dimension.
First, a new path to promote Moore's Law
As we all know, Moore's Law was conceived half a century ago by Gordon Moore, one of Intel's founders. The content is, "When the price is constant, the number of transistors that can be accommodated on an integrated circuit doubles approximately every 18-24 months." ”
Over the past few decades, the semiconductor process process has basically followed Moore's Law in continuous advancement, the size of transistors is also constantly shrinking, and the performance of processors has been continuously enhanced, while the cost remains unchanged, and even can be reduced. However, as the process node continues to advance towards the smaller 5nm, 3nm and even The Amy level, it is getting closer and closer to the physical limit, not only the difficulty of propulsion is getting higher and higher, but the price to be paid is also increasing.
For example, 5nm and below processes must use ASML's EUV lithography machine, and an EUV lithography machine is priced at about $150 million, an investment in a 5nm fab is often tens of billions of dollars, and the cost of a 5nm chip is as high as tens of millions of dollars. ASML's new generation of High-NA EUV lithography machines, which can be used for 2nm chip manufacturing, may sell for up to $300 million per unit.
Therefore, a few years ago, two major wafer foundries, UMC and GF, announced that they would abandon the research and development of advanced processes below 10nm. Even Intel, the number one practitioner of Moore's Law, has suffered serious delays in advancing from 14nm to 10nm and 10nm to 7nm. The industry's perception of "Moore's Law slowing down" or "Moore's Law is dead" is also very common.
However, TSMC, Intel, Samsung and other leading wafer manufacturers are still committed to promoting the continuation of "Moore's Law". Both TSMC and Samsung plan to mass-produce 3nm next year. Intel is also accelerating its catch-up and has set a target of mass production of 20A (2nm) by 2024.
Luo Zhenqiu, general manager of TSMC (Nanjing) Co., Ltd., said, "TSMC is using our process to prove that the semiconductor process process is still moving forward. TSMC's 7nm was launched in 2018, 5nm was launched in 2020, we will launch the 3nm process as scheduled in 2022, and our 2nm process is also in smooth development. In the future, we can continue to promote the optimization of transistor efficiency by changing the structure of transistors and introducing new materials. ”
However, "Moore's Law" is not just about increasing the number of transistors per unit of time, but also about keeping the price constant or lowering. But in fact, as advanced processes continue to advance, the rate of cost reduction per unit transistor is slowing down.
According to the information previously released by Intel, from the cost point of view, with the advancement of advanced processes, although the cost per square millimeter of chips is rising, but with the increase in transistor density, the chip area occupied by the same number of transistors is declining, so overall, the cost of unit number of transistors has not only not increased, but has been declining. For example, Intel's 14nm and 10nm processes and 7nm processes will bring about a decline in the cost of transistors, but the decline is already accelerating and slowing down compared to before.
In addition, the research institute IBS previously compared the cost of transistors from 16nm to 3nm through relevant statistics and forecasts, and we can also see that with the advancement of the process process, the decline in the cost of unit number of transistors is decreasing sharply. For example, from 16nm to 10nm, the cost per 1 billion transistors has decreased by 23.5%, while the cost from 5nm to 3nm has decreased by only 4%.
This also means that the "economic benefits" brought about by the continued promotion of "Moore's Law" are sharply decreasing. And that's the crux of the matter.
Zhang Jingyang, chairman and CEO of Moore Elite, also said: "Moore's Law actually has two explanations, one is from the technical level, the density of transistors per unit area should be doubled; the other explanation is that double the computing power should be bought with the same money, which is a systematic concept." In fact, the customer really does not care about how advanced your technology is, he is concerned about how to spend the same money to get better performance. ”
Indeed, what is needed for users is not a doubling of the number of transistors every two years brought about by Moore's Law, but an overall increase in system-level performance and a constant or reduction in cost. The performance at the system level is determined by many computing units such as CPU/GPU/DSP/NPU, as well as memory capacity, bandwidth, system software and many other links.
Therefore, in recent years, the industry has also proposed new technologies and methodologies such as Chiplet and 2.5/3D advanced packaging, hoping to promote the increase in the number of transistors per unit area on a single silicon wafer from simply relying on the improvement of increasingly costly process processes, to improving the overall performance and function through a complex system-on-chip design with relatively controllable costs, so as to achieve the performance and cost relationship of system-level chips to continue to maintain the "economic benefits" of Moore's Law.
At the 2021 SNUG World User Conference (SNUG World 2021), the concept of "SysMoore" proposed by Aart de Geus, co-CEO and founder of EDA Company Synopsys, is also based on this background.
The so-called "SysMoore" is to expand the concept of improving the degree of integration and complexity to every aspect of the electronic system, from silicon wafers, transistors, chips, system hardware to software and services, each link can contribute to the construction of more complex, higher performance, lower energy consumption and better cost of the product, developers no longer rely only on a few dimensions such as technology and architecture to achieve exponential improvement of performance and complexity, after the indicators are dispersed to different links to undertake, The growth curve of electronic system performance and functional complexity returns to an exponential growth trajectory. This coincides with the previously mentioned concept of continuing the economic benefits of "Moore's Law" from the system chip level through chipset, advanced packaging and other technologies.
"Chiplet and advanced packaging can't do this thing to double the density of transistors per unit area, and must rely on process process iteration." But how to get more transistor count and performance for the same money, this is what Chiplet and advanced packaging can do. Currently, the Moore elite is also working on SiP packaging. Zhang Jingyang said.
Second, what is Chiplet and what are the advantages?
Chiplet is not a new technology, as early as 2015, Marvell founder Dr. Sehat Sutardja proposed the MoChi (Modular Chip) concept at ISSCC 2015. Subsequently, AMD implemented chiplet designs with the goal of balancing performance, power consumption and cost, and proposed performance/W and performance/$ measurement standards.
At present, the mainstream system-level single-chip (SoC) is to be responsible for different types of computing tasks of the calculation unit, through the form of lithography to the same wafer. For example, the current flagship smartphone SoC chip, basically integrated CPU, GPU, DSP, ISP, NPU, Modem and many other different functions of the computing unit, as well as a lot of interface IP, the pursuit of a high degree of integration, the use of advanced processes for all units to comprehensively improve.
The "Chiplet" is the opposite, it is the original complex SoC chip, from the design of the first according to different computing units or functional units to decompose it, and then each unit to choose the most suitable semiconductor process process for manufacturing separately, and then through advanced packaging technology to interconnect each other, and finally integrated packaging into a system-level chipset.
For "Chiplet", many people call it "small chip". In this regard, Dr. Dai Weimin, founder, chairman and president of VeriSilicon, believes that this is not accurate, because some Chiplets are not small, and there is no unified name in the industry at present, and he believes that it is relatively accurate to call "core grains".
Dai Weimin said: "Chiplet is expected to solve the current four major problems facing the semiconductor industry: 1, Moore's Law is unsustainable; 2, the design cost and complexity of advanced process chips have increased significantly; 3, the market demand is more diversified, the innovation cycle is shortened; 4, the demand for customized chips at the application side is constantly improving." ”
So why did Chiplet solve these problems? What are its advantages?
First, Chiplet can greatly improve the yield of large chips. At present, the huge demand for computing in high-performance computing, AI and other aspects has promoted the rapid increase in the number of computing cores in the logic chip, at the same time, the supporting SRAM capacity and I/O number are also greatly improved, making the entire chip not only the number of transistors soar, but also the area of the chip continues to increase.
For example, Cerebras Systems, a chip startup that launched the "world's largest" AI chip Wafer Scale Engine ("WSE") in 2019, launched a new WSE-2 processor in April this year, still based on a single 12-inch wafer. With an area of up to 462.25 square centimeters, the process has been upgraded from TSMC's 16nm process to 7nm process, which has also increased the number of transistors of WSE-2 to a staggering 2.6 trillion.
With the continuous growth of chip area, not only does it increase the difficulty of manufacturing, but also the loss caused by its inherent defect rate is also increasing. For example, if a WSE-2 chip is not good, it is equivalent to directly losing an entire wafer.
Through the Chiplet design, the very large chip can be cut into independent small chips according to different functional modules and manufactured separately, which can not only effectively improve the yield, but also reduce the cost increase due to the defect rate.
Second, Chiplet can reduce the complexity and cost of the design. With the continuous advancement of advanced processes, the complexity and design difficulty of chips based on more advanced processes will also increase significantly, and the design cost will also rise sharply. If the chip is designed and there is not enough shipment, it will undoubtedly face huge losses. If the large-scale SoC is decomposed into core particles according to different functional modules in the chip design stage, then some core particles can achieve similar modular design and can be reused in different chip products. This can greatly reduce the difficulty and design cost of chip design, and is also conducive to the iteration of subsequent products and accelerates the market cycle of products.
In this regard, Dai Weimin also proposed the concept of "IP chip", that is, some semiconductor IP cores are provided in the form of silicon wafers, IP is the core particle, aiming to achieve the "plug and play" and "reuse" of IP in the form of core particles, in order to solve the contradiction between the performance and cost faced by the original advanced process chip, and reduce the design time and risk of large-scale chips, and realize the IP presented in the form of independent core particles from IP in SoC to SiP package.
For many SoC manufacturers, when designing a large SoC chip, a large number of third-party IP needs to be integrated with their own IP to form a unified SoC, and then manufactured using the same process. If the Chiplet mode is adopted, then only need to design their own core "core particles", manufactured by the appropriate process process, other core particles do not need to be designed, manufactured, and do not need to be bound to the process process selected by their own core "core particles", chip designers can directly select a third party based on the appropriate process of the "core particles" to provide IP, and then through advanced packaging technology to package the core particles together, you can. This can greatly reduce the difficulty of chip design, improve flexibility and efficiency.
Third, reduce the cost of chip manufacturing. As mentioned earlier, there are different computing units in a SoC, but also SRAM, various I/O interfaces, analog or digital-analog hybrid components, the main reason is that the logic computing unit usually relies on advanced processes to improve performance, while other parts of the process requirements are not high, and some can play a good performance even if they use mature processes. Therefore, after chipletizing the SoC, different core particles can choose the appropriate process according to their needs, to manufacture separately, and then assemble through advanced packaging technology, without all of them using advanced processes to manufacture on a wafer, which can greatly reduce the manufacturing cost of the chip.
Because Chiplet has many advantages, in recent years, AMD, Xilinx, Intel and other large chip manufacturers have begun to use chiplet architecture in related products.
Taking AMD as an example, it fully adopts the Chiplet architecture in the Zen 2 product line launched in 2019, and the biggest feature of its chip design is to separate the I/O module from the logic operation module, and the I/O module continues to use the 12nm process, while the logic operation module adopts the 7nm process.
For example, in August this year, Intel launched a super-large-scale chip with 100 billion transistors - Ponte Vecchio, the most complex chip to date, using the Chiplet architecture, the entire 47 different function units, through different process processes manufactured (for example, each of the Ponte Vecchio's computing units Xe-Core is based on TSMC's 5nm process, but the Xe link unit is manufactured by TSMC's 7nm process). And then packaged together via Intel's Coveros 3D technology.
Some analyses have shown that if a large 7nm chip is designed using the Chiplet architecture, its cost can be reduced by more than 25% compared with the original.
In addition, some market research companies believe that compared to traditional SoC designs, Chiplet can reduce the overall manufacturing cost by nearly 50%, and this cost advantage is more obvious in products with more computing cores.
In addition to the traditional HPC market, Dai Weimin believes that Chiplet is very suitable for automotive self-driving chips. Because the current automotive autonomous driving chip has very high requirements for computing power, the area of the chip is very large, the cost is very high, and using Chiplet to do it can not only reduce the design difficulty, improve the yield, reduce the design and manufacturing costs, but more critically, it can also provide higher safety and rapid iteration.
"Automotive chips have very high safety requirements, and the certification cycle of the car standard level is very long, and Chiplet is to decompose a large chip into many core particles, even if one or two core particles have problems, but others may still work normally." Once the traditional large chip fails, it is dangerous to directly go down. In addition, the design cycle of large chips is long, and each iteration needs to be re-certified, but if the Chiplet design is adopted, then each iteration only needs to replace or add a few more core core particles to achieve, which can achieve rapid iteration under the premise of ensuring safety. Dai Weimin explained.
Third, chiplet faces the problem
Although Chiplet has many benefits, it still faces many challenges and challenges that need to be solved to make the most of its effectiveness.
1, advanced packaging technology is the key
For Chiplet, the key is advanced packaging technology, so that each "Chiplet" is interconnected at high speed and integrated into a system-on-chip.
Although the current widely used SiP (System in Packaging, system-in-package) technology is also through the integration and packaging between different components, Chiplet has higher requirements for packaging technology, because each core particle requires high-density interconnection to achieve high-speed interconnection, similar to the signal transmission speed between each functional module in the original single large chip.
At present, the leading IDM manufacturers, wafer foundries and OSAT manufacturers are actively promoting different types of advanced packaging technologies to seize this market. At present, the packaging solutions that can be applied to Chiplet are mainly 2.5D and 3D packages.
Among them, the development of 2.5D packaging technology has been very mature, and has been widely used in FPGA, CPU, GPU and other chips, in recent years, with the rise of Chiplet architecture, 2.5D packaging has also become the main packaging solution for Chippet architecture products. Its biggest feature is the use of Interposer (intermediary layer) as an integrated medium, mainly used as a communication interconnection between the small chips placed on it, and the connection between the chips and the carrier board.
In addition, there is HD-FO (High density Fan-out) packaging technology, which is still only used in the integration of more basic heterogeneous components (such as the integration of logic ICs and HBM), but as technology continues to advance with its low cost advantages, there may be an opportunity to further become another packaging option for Chiplet adopters in the future.
Overall, however, the new 3D packaging technology is better suited to Chiplet, which can help enable 3DIC, i.e. stacking between cores and high-density interconnects, providing more flexible design options. However, the technical difficulty of 3D packaging is also higher, and at present, Intel and TSMC master 3D packaging technology and have commercial use.
As early as 2017, Intel launched the EMIB (Embedded Multi-Die Interconnect Bridge, embedded multi-core interconnect bridge) packaging technology combined, which can flexibly combine different types and different processes of small chip IP in the form of 2.5D to form a SoC-like structure.
At the Intel Architecture Day event at the end of 2018, Intel launched the industry's first 3D logic chip packaging technology - Foveros 3D, which enables stacking logic chips of different processes on logic chips. Previously, logic chips and memory chips could only be connected together, because the bandwidth and data requirements in the middle were lower. The Coveros 3D can stack logic chips of different processes together, the interconnection gap between the dies is only 50μm, and the bandwidth of the connection is large enough, the speed is fast enough, the power consumption is low enough, and the 3D stacked package form can also maintain a small area. In July, Intel also announced plans to launch Coveros Direct technology, which can achieve bump spacing below 10 microns, increasing the interconnect density of 3D stacks by an order of magnitude.
Previously, Adel Elsherbini, chief engineer of the component research department of Intel's packaging research division, said in an interview with Chip Intelligence that Intel's 3D packaging technology can help chip designers connect small chips with different functional attributes from the SoC system on a chip at high speed and integrate them in the same package, through which performance and functionality close to that of a single chip can be achieved.
In addition to Intel, TSMC has also been laying out 2.5/3D packaging technology for a long time.
Luo Zhenqiu, general manager of TSMC (Nanjing) Co., Ltd., told Chip Intelligence that in terms of 2.5/3D packaging, TSMC has been laid out for more than 10 years. At present, TSMC has integrated advanced package-related technologies into the "3DFabric" platform, for the front-end integrated system-on-chip (SoIC), for the rear-end package of the integrated fan-out (InFO), and the CoWoS family family.
Luo Zhenqiu told ChipTech: "If at the press conference of some chip companies, see that his package area is greater than 20mm × 20mm, then it is likely to be made of TSMC 2.5D package or 3D packaging technology." In the future, we will continue to see more products using TSMC's 3D packaging technology, which not only has a smaller area, but also has stronger performance. ”
Samsung is also pushing its 2.5/3D package technology. Samsung introduced the 2.5D packaging technology I-Cube very early, which integrates one or more logic chips (such as CPUs, GPUs, etc.) and multiple memory chips (such as high-frequency wide memory, HBM) on top of the silicon interposer, further enabling multiple chips to work for integration into a single component. In August 2020, Samsung announced the launch of a new generation of 3D packaging technology - X-Cube, based on TSV silicon perforation technology to stack different chips, such as SRAM stacked on top of the chip, freeing up space, can be stacked more memory chips, can now be used for 7nm and 5nm processes.
At present, domestic IDM, wafer foundries and packaging and testing foundries are also actively laying out 2.5D/3D packaging technology, but the progress is relatively backward compared with foreign manufacturers. For example, Changdian Technology, a major domestic packaging and testing factory, is also vigorously promoting the mass production of its 2.5D packaging technology.
2. Design and verification tools
First of all, for chip design, although there is no need to design complex large chips, the soC decomposition Chiplet and integration into a 2.5/3D package will bring about a significant increase in system complexity and will bring greater system design and verification challenges.
Compared with the original 2D single chip, the design and packaging are completely independent. Chiplet and 2.5/3D package combination, its internal core particles may use different processes, different architectures, but also need to add high-speed interconnection bus, interface IP, HBM memory, each module may also need to use different materials for interconnection, therefore, in the chip design, it is necessary to see the internal package of each module as a whole system, you need to consider the design and optimization of the entire system level at the beginning.
Especially for 3DIC, from the outside, it is a "black box" inside, and the test probe can only pass through some points on the surface to a limited amount of data, which also brings great challenges to the analysis and testing of 3DIC.
Xu Wei, deputy general manager of Synopsys China, introduced to Chip Intelligence: "As the chip manufacturing process continues to approach the physical limit, the layout design of the chip - heterogeneous integrated 3DIC advanced packaging has become one of the best ways to continue Moore's Law. However, as a new field, 3DIC did not have a mature design analysis solution before, and the use of traditional disconnected point tools and processes would bring great challenges to design convergence, and the demand for signal and power integrity analysis also exploded with vertically stacked chips. ”
Wang Xiaoyu, General Manager of Cadence China, also said: "There are many challenges in 3DIC, and integrating different core particles through 2.5/3D packages needs to be regarded as a complete system to achieve integrated design simulation. Taking into account the signal integrity, thermal power consumption, continuous convergence, physical verification, and so on, these are all challenges. ”
In this regard, EDA manufacturers such as Synopsys Technology, Cadence, and Siemens EDA have also carried out corresponding layouts.
In August 2020, Synopsys introduced the 3DIC Compiler platform, which enables the design and integration of complex 2.5D and 3D multi-die systems in a single package. At the same time, Synopsys also jointly launched the industry's first unified platform for 3DIC multi-chip system design analysis together with core and semiconductor, seamlessly combining the 2.5D/3DIC advanced package analysis solution Metis of domestic EDA manufacturer core and semiconductor with the existing design process of Synopsys 3DIC Compiler, building a fully integrated, outstanding performance and easy-to-use environment for customers, providing a range of development, design, verification, signal integrity simulation, Power integrity simulation to final sign-off of the 3DIC full-process solution. It breaks through the limits of traditional packaging technology and can support the interconnection of hundreds of thousands of data channels between chips at the same time.
In October 2021, Cadence also launched the industry's first complete high-capacity 3D-IC platform, unifying design planning, physical implementation, and system analysis in a single management interface. The Integrity 3D-IC platform supports Cadence's third-generation 3D-IC solution, allowing customers to optimize system-driven Chipt's power, performance, and area objectives (PPA) with integrated thermal, power, and static timing analysis capabilities.
Wang Xiaoyu said: "We believe that this is an epoch-making product, the industry's first truly integrated 3DIC design and development platform. There were many solutions before, which were to put together different solutions for each company. And our solution, all of which are our tools, there are analog, there are digital, there are PCBs, there are packages, and the system set simulation analysis tools, multiphysics analysis tools, 3DEM, thermal power consumption, convergence analysis, this platform will rise to a unified database work. ”
Although Siemens EDA (formerly Mentor) has not officially launched an EDA tool platform specifically for 3DIC, Siemens EDA has long been deploying 3DIC solutions.
Ling Lin, global vice president and general manager of Siemens EDA in China, told ChipTech that as early as seven or eight years ago, Siemens EDA provided a lot of EDA tool support for customers' 2.5D and 3D heterogeneous integrated packages. The current 3DIC multi-chip system blurs the boundaries between IC and PCB design technology.
"Siemens EDA is not only the world's top three IC design tool manufacturers, but also the world's largest PCB design tool manufacturers, whether based on the board set or based on silicon substrate to do 2.5D or 3D stacking, we can support very well." And as early as seven or eight years ago, we have launched the corresponding tools for design and production enterprises to use. Two years ago, we also had AMD-enabled Chiplet CPU GPUs in TSMC. Ling Lin said.
Compared with the three major EDA head manufacturers in the 3DIC design verification tool have successively launched various types of powerful products, although the domestic EDA manufacturers are relatively backward in technical strength and volume, but also actively layout the 3DIC market.
For example, the aforementioned domestic EDA manufacturer Core and Semiconductor has launched a 2.5D/3DIC advanced package analysis solution Metis, and has been recognized by Synopsys Technology, and the two sides have also reached in-depth cooperation in this regard.
Yang Ye, product and business planning director of domestic EDA manufacturer Chip Huazhang Technology, said: "From the perspective of front-end design and verification, chiplet also needs an 'EDA for Chiplet' design and verification process, as well as supporting tools. The current SoC can build a system prototype in the design stage for functional power consumption and other verification, if the chiplet is used, how to cooperate between EDA manufacturers, chiplet manufacturers and chip manufacturers will be one of the new challenges in the development of chiplet. At present, The core Huazhang has begun some layout, but the first direction to look at is the storage field. ”
Wang Chengyu, CTO of Hongxin Micro-nano, another domestic EDA manufacturer, also said, "In the post-Moore era, Chiplet is an important direction, if we pay attention to the immediate situation and do not go to the earlier layout, we may wake up and the market has turned." And some of the customers we work with also have this demand, so we started the layout very early. ”
"Our initial plan will be divided into two steps, the first is to do the stacking between Die and Die, there will be basic like 3DIC timing analysis capabilities, and how to build the model of the connection between Die and Die, this is the first step; the second step is system-level optimization to achieve better performance effects, which will involve layout and routing from plane to 3D." After that, we provide tools for the digital backend, power analysis tools, EMR analysis tools, and so on. Wang Chengyu introduced.
3. Interconnection and standards between Chiplets
Chiplet is to break the original system chip into a plurality of independent core particles, and to integrate these core particles through advanced packaging technology, it is also necessary to be able to interconnect at high speed, and how to achieve high-speed interconnection between each core particle is a problem that needs to be solved.
For example, Marvell used the Kandou bus interface when introducing the modular chip architecture; NVIDIA's high-speed interconnection NV Link program for GPUs; Intel's free licensing of the AIB advanced interface bus protocol; TSMC and Arm cooperated in the LIPINCON protocol; AMD also has Infinity Fabrie bus interconnection technology, and the HBM interface for memory chip stack interconnection.
It can be seen that at present, these are the head chip design companies to promote their own high-speed interconnection protocol standards, and they are mainly used in their own chips. However, with the gradual development of Chiplet, the interconnection demand between core particles from different manufacturers will inevitably explode in the future. Especially for IP manufacturers, their business model may shift from selling IP to "IP chipping", that is, IP is "core grain".
Therefore, in recent years, many industry organizations, research institutions and enterprises have been actively promoting chiplet standards.
For example, in October 2018, the Open Computing Project (OCP) launched a new team called Open Domain Specific Architecture (ODSA) with the goal of developing a Chiplet open standard, facilitating the Chiplet ecosystem, and spawning low-cost SoC alternatives.
In 2019, DARPA (U.S. Defense Advanced Research Projects Agency) in the United States also launched the "CHIPS" program. The vision of the project is to create an industry-wide ecosystem of independently modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies.
It is also understood that there are also relevant manufacturers in China that are promoting China's Chiplet standard.
Dai Weimin told Chip zhixun: "I think Chiplet is to be able to connect with each other, which of course the standard is very important, but if we do our own Chiplet standard behind closed doors, this may go astray." Because the starting point of the standard is to let everyone be better connected, but not to form a variety of different standards, artificially causing interconnection is not smooth. Therefore, this standard needs to be reached by the entire industry, even if there are different standards, it also needs to be compatible. Because the more advanced the process of Chiplet, after doing a good job, if you want to change it again, this cost is huge. ”
"On the chiplet ecology, I think we need to be compatible with the external ecology even if we want to do our own standards. Our company also has its own Chiplet protocol, and some time ago Intel also came to us, hoping that we can be compatible with Intel's AIB protocol, because our set of solutions also happens to be parallel (Chiplet has serial and parallel solutions). If we can be compatible with the AIB protocol, such as some FPGA users, because they will support the AIB interface on the new FPGA, if we have compatibility, we can let users realize the interconnection of ASICs and FPGAs. Therefore, we also feel the need to be compatible with more ecology, so that the chips can better achieve high-speed interconnection, should not hold a very closed mentality to do this thing. The technical leader of a domestic semiconductor IP manufacturer said to The Core Intelligence.
4. Test
For Chiplet, splitting a large SoC chip into multiple core particles can improve chiplet's yield better than a single large SoC, but it will also lead to more testing work. Testing of many core particles needs to be done at the wafer stage, which requires more probes to complete the test at the same time.
At the SEMICON TAIWAN 2021 online forum at the end of December, Xie Chengru, former general manager of Intel Innovation Technology, also said that with the current chip complexity and more complex packaging, it is necessary to test the technology correspondingly. It's like running in the forest with your eyes closed, it's going to be very difficult. Chiplet Challenges For probe cards, in order to maintain a higher final yield, the test of splitting four small wafers in a system must be completed in the wafer test section, and more probe cards are needed to complete the test at the same time.
Xie Chengru also mentioned that heterogeneously integrated Chiplets have more variables than a single chip manufacturing, requiring more accurate classification tests in wafer test segments to avoid the final performance degradation, which requires the industry to work together to overcome.
Editor: Xin ZhiXun - Langke Sword