According to consultancy Yole Developpement, semiconductor manufacturers' capital expenditures in advanced packaging will be about $11.9 billion in 2021.
The agency said that the advanced packaging market volume is about $2.74 billion in 2021, and predicts that the market will achieve a compound annualized growth rate of 19% by 2027, when the advanced packaging market volume will reach $7.87 billion per year.
According to the agency, Intel will invest $3.5 billion in 2021 to support the development of its advanced packaging technologies Coveros and EMIB.
Other major players include TSMC, which has invested $3.05 billion in the field, and Sun Moon, which has invested $2 billion. With its FoCoS product, Sun Moonlight is currently the only OSAT with an ultra-high density fan-out solution.
(From Intel)
This article was compiled by the semiconductor industry from seminalysis
Advanced packaging is present in a continuum of cost and throughput and performance and density. In the first part of this series (a very detailed interpretation of advanced packaging), we talked about the need for advanced packaging. While the need for advanced packaging is obvious, from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/ LPDDR DRAM, CIS), Sun Moon (FoCoS, FOEB), Sony (CIS), Micron (HBM), SK Hynix (HBM) and XStacking have an astonishing number of advanced package types and brands. Companies like AMD and Nvidia that we talk about a lot also use these packaging types.
In this article, we will explain all of these types of encapsulation and their purpose.
Flip chip is one of the common packaging forms after lead bonding. It is offered by numerous companies from foundries, integrated design manufacturers, and outsourced assembly and testing companies. In flip chips, the PCB, substrate, or other wafer will have a landing pad. The chip is then placed precisely on top, the bulge is in contact with the landing pad, and then the chip is sent to a reflow furnace, which heats the components and reflows to the bump, gluing the two together. The flux is then removed and the underfill is deposited between the two. This is just a basic process flow, there are many different types of flip chips, including but not limited to flux-free.
While flip chips are very common, advanced versions with pitches smaller than 100 microns are less common. Regarding the definition of advanced packaging that we established in Part 1, only TSMC, Samsung, Intel, Amkor, and ASE involve a large number of logical advanced packages using flip chip technology. Three of these companies are also manufacturing complete silicon wafers, while the other two are outsourced assembly and testing (OSAT).
This is where a large number of different types of flip chip package types start to emerge. We will take TSMC as an example, then expand and compare other companies' packaging solutions with TSMC's packaging solutions. The biggest differences across all of TSMC's package options are the substrate material, size, RDL, and stacking.
In standard flip chips, the most common substrate is usually an organic laminate, which is then coated with copper. From here, wiring is built around the core on both sides, with the most discussed Amanomoto laminar membrane (ABF). The core builds a number of layers on top that are responsible for redistributing signal and power throughout the package. These signal-carrying layers are patterned using dry film lamination and using a CO2 laser or UV laser.
This is where TSMC's expertise begins to play a role in integrated fan-out (InFO). Instead of using the standard process of ABF films, TSMC uses a process that is more relevant to silicon fabrication. TSMC will use the Tokyo Electronic Coater/Developer, ASML Lithography Tool, and Applied Materials Copper Deposition Tool to lithographily define the redistribution layer. The redistribution layer is smaller and denser than most OSAT can produce, and therefore can accommodate more complex cabling. This process is called fan-out wafer level packaging (FOWLP). ASE is the largest OSAT, offering FoCoS (Fan-Out Chip on Substrate), a form of FOWLP that also leverages silicon manufacturing techniques. Samsung also has their Fan-Out System Package (FOSiP), which is mainly used in smartphones, smartwatches, communications and cars.
With InFO-R (RDL), TSMC can package chips with high IO density, complex cabling, and multiple cores. The most common products to use InFO-R are Apple's iPhone and Mac chips, but there are also a wide variety of mobile chips, communication platforms, accelerators, and even network switch ASICs. Samsung also won the ass fan out of the market with the Cisco Silicon One in the network switch ASIC. Advances in The InFO-R are primarily related to larger package sizes with more power consumption and IO.
There are many rumors that AMD will provide fan-out encapsulation for its upcoming Zen 4 client (pictured above) and server CPUs. SemiAnalysis can confirm that Zen 4-based desktop and server products will use fan-out. This fan-out will then be traditionally packaged on top of a standard organic substrate with LGA pins on the bottom. The companies that encapsulate these products and the technical reasons for turning to fan-out will be revealed later.
The standard package will have a core substrate and then a 2 to 5-stage redistribution layer (RDL) on each side, including a more advanced integrated fan-out. TSMC's Info-SoIS (Integrated Substrate System) takes this concept to the next level. It offers up to 14 redistributive layers (RPLs) for very complex wiring between chips. There is also a higher density wiring layer on the substrate close to the die.
TSMC also offers Info-SOW (System on Wafer), which allows fanning out the size of an entire wafer that can encapsulate dozens of chips. Tesla Dojo1, it takes advantage of this special form of packaging. Tesla will also use Samsung FOSiP on HW 4.0.
Finally, in TSMC's integrated fan-out lineup, there is InFO-LSI (Local Silicon Interconnect). The InFO-LSI is an InFO-R, but there is a piece of silicon underneath multiple chips. This local silicon interconnect will start as a passive interconnect between multiple chips, but it could evolve into active (transistors and various IPs) in the future. It will eventually shrink to 25 microns as well, but we don't think that's going to happen with the first generation. The first product in this package will be shown later.
The most immediate comparison that comes to mind is probably Intel's EMIB (Embedded Multichip Interconnect Bridge), but it's not the best option. It's more like Intel's Coveros Omni or ASE's FOEB. Let's explain.
Intel's embedded multi-chip interconnect bridge is placed in a traditional organic substrate cavity and then proceeds to build the substrate. While this can be done by Intel, the placement and construction of EMIB can also be done by traditional organic substrate vendors. Due to the large pads on the EMIB chip, as well as the method of depositing laminated wiring and through holes, there is no need to place the chip extremely precisely on the substrate.
Intel is abandoning more expensive silicon substrate materials and silicon manufacturing processes by continuing to use its existing supply chain of organic laminates and ABF. Although currently very tight due to shortages, in general, this supply chain is commoditized. Intel's EMIB has been shipping since 2018, including the Kaby Lake G, various FPGAs, Xe HP GPUs, and certain cloud server CPUs including Saphire Rapids. All CURRENT EMIB products use 55 microns, but the second generation is 45 microns and the third generation is 40 microns.
Intel can push power through this chip to the active chip above. Intel also has the flexibility to design the package to run without EMIB and some chiplets if needed. After the teardown of the Intel FPGA, it was found that Intel would not place EMIB and active chips if the SKU shipped by Intel was required. This allows for some optimization around the BOM of certain parts. Finally, Intel can also save on manufacturing costs by using silicon bridges only where they are needed. This is in stark contrast to TSMC's CoWoS, where all of its chips are placed on top of a single large passive silicon bridge. More on that later, but the biggest difference between TSMC's Info-LSI and Intel's EMIB is the choice of substrate materials and manufacturing processes.
To complicate matters further, Sun Moonlight also has its own 2.5D package technology, which is very different from Intel's EMIB and TSMC's Info-LSI. It is used in AMD's MI200 GPU, which will be used in multiple high-performance computers, including the U.S. Department of Energy's Frontier exascale system. ASE's FOEB packaging technology is more similar to TSMC's InFO-LSI in that it is also fan-out. TSMC uses standard silicon manufacturing techniques to build RDL, with one major difference being that ASE uses glass substrate panels instead of silicon. It's a cheaper material, but it has some other benefits that we'll discuss later.
Instead of embedding a passive interconnect die into the cavity of the substrate, the ASE places the die, builds a copper column, and then builds the entire RDL. On top of the RDL, the active silicon GPU chip and the HBM chip are connected using micro-bumps. The glass interlayer is then removed from the package using a laser release process, and then the other side of the package is completed before it is mounted onto the organic substrate using the standard flip chip process.
The ASE has many ideas about FOEB and EMIB, but some of them are completely wrong. It's understandable that ASE needs to market their solution, but let's filter out the noise and look again. EMIB yields are not in the range of 80% to 90%, emib yields are close to 100%. The first generation OF EMIBs did have scaling limits in terms of the number of chips, but the second generation did not. In fact, Intel will release the largest package ever, an advanced package in the 92mm x 92mm BGA package of the second-generation EMIB. By using RDL defined by fan-out and lithography throughout the package, FOEB does retain advantages in terms of routing density and chip-to-package bump size, but it is also more expensive.
Compared to TSMC, the biggest difference seems to be the original glass substrate material with silicon. Part of the reason may be due to the more limited cost of ASE. ASEs must win over their customers by providing excellent technology at a lower cost. TSMC is a chip master, focusing on the technology they are familiar with, TSMC has a culture of pushing technology to the extreme, and under this impetus, they are better off choosing silicon.
Now back to TSMC's other advanced package options. The CoWoS platform also has the CoWoS-R and CoWoS-L platforms. They correspond almost one-to-one to InFO-R and InFO-L. The difference between the two has more to do with the process. InFO is a chip-first process that first places the chip and then builds the RDL around which it is built. With CoWoS, the RDL is built first, followed by the chip. This distinction is not so important for most people trying to understand advanced packaging, so today we will discuss this topic with relative ease.
Most notably, CoWoS-S (Silicon Intermediation Layer). It involves taking a known-good chip, encapsulating its flip chip onto a passive wafer with patterned wires on it. That's where the name CoWoS comes from, Chip on Wafer on Substrate. It is currently the largest 2.5D package platform in capacity. As mentioned in Part 1, this is because NVIDIA data center GPUs such as the P100, V100, and A100 use CoWoS-S. While Nvidia has the highest sales, broadcom TPUs, Amazon Trainium, NEC Aurora, Fujitsu A64FX, AMD Vega, Xilinx FPGAs, Intel Spring Crest, and Habana Labs Gaudi are just a few notable examples of CoWoS use. Most heavy-duty chips that use HBM computing, including AI training chips from various startups, use CoWoS.
To further highlight the popularity of CoWoS, we're going to talk about AIchip. AIchip is a Taiwanese design and IP company that leverages TSMC's CoWoS platform for EDA, physical design, and capacity work related to AI chips.
TSMC didn't even attend all the meetings related to CoWoS capacity because TSMC already sold all the products they made, and it took too much engineering time to support all of those designs. On the other hand, TSMC's customer concentration is high, so TSMC wants to cooperate with other companies. AIchip is a bit like a middleman, and even though Tier 1 customers have booked everything, AIchip still gets some inventory. But they can only get 50% of what they want.
Let's take a look at what NVIDIA is doing. In the third quarter, their long-term supply payments jumped to $6.9 billion, and more importantly, Nvidia prepaid $1.64 billion and will pay another $17.90 in the future. Nvidia is supplying capacity in large quantities ahead of schedule, especially for CoWoS.
Returning to technology, CoWoS-S has evolved over the years, marked by a larger intermediary area. Since the CoWoS platform uses silicon manufacturing technology, it adheres to the principle of "reticle restriction". The maximum chip size that can be printed with the 193nm ArF lithography tool is 33mm x 26mm (858 mm2). The silicon interlayer is lithographed to define its main use, which is to connect the very dense wires of the chip located on top of it. NVIDIA's chip itself is already close to the reticulate limit, but still needs to be connected to the package's high-bandwidth memory.
The image above contains the Nvidia V100, a GPU introduced by NVIDIA 4 years ago and with an area of 815 square millimeters. Once HBM was included, it went beyond the limits of the reticles that lithography tools could print, but TSMC figured out how to connect them. TSMC achieves this through the method of reticle stitching. TSMC has enhanced their capabilities here to provide a 3x size mask for the silicon interposer. Given the limitations of reticle stitching, the Intel EMI, TSMC LSI, and ASE FOEB methods have advantages. They also don't have to pay a high fee for a large silicon intermediary layer.
In addition to increasing the mask plate size, they also made other improvements, such as changing the micro-bump from solder to copper to improve performance/power efficiency, iCap, new TIM/lid package, etc.
There is an interesting story about tim/lid encapsulation. With the Nvidia V100, NVIDIA has a ubiquitous HGX platform that will ship to many server ODMs and then send them to data centers. The torque that can be applied to the cooler screws to achieve the correct mounting pressure is very specific. These server ODMs over-tighten coolers and chips on these $10,000 GPUs. Nvidia swapped their A100 into a package that has a lid on the chip instead of direct chip cooling. This packaging problem arises when Nvidia's A100 and future Hopper DC GPUs still need to dissipate a lot of heat. TSMC and NVIDIA had to do a lot of optimizations on the package to solve this problem.
Samsung also has I-Cube technology similar to the CoWoS-S. Samsung's only major customer using this package is Baidu's artificial intelligence accelerator.
Foveros technology
Next we introduce Flourlos, which is Intel's 3D chip stacking technology. Foveros is not one chip active on another, but rather that the other chip is essentially just dense wires, Foveros involves two chips containing active components. With this, Intel's first-generation Coveros was launched in the Lakefield Hybrid CPU SOC in June 2020. The chip isn't particularly large in capacity or breathtaking, but it's one of Intel's many firsts, including a 3D package and their first hybrid CPU core architecture with high-performance cores and small-efficiency cores. It uses a bump spacing of 55 microns.
The next Coveros product is the Ponte Vecchio GPU, which, after multiple delays, should be available this year. It will include 47 different active chiplets packaged with EMIB and Coveros. Foveros chip-to-chip connections use a 36-micron bump pitch.
In the future, most of Intel's client lineup will use 3D stack technology, including client products code-named Meteor Lake, Arrow Lake, and Lunar Lake. Meteor Lake will be the first to feature the Foveros Omni and 36 micron bump pitch. The first data center to include 3D stack technology was codenamed Diamond Rapids, which followed Granite Rapids. In this article, we will discuss which nodes some of these products use and Intel's relationship with TSMC.
The full name for Foveros Omni is Coveros Omni-Directional Interconnect (ODI). It bridges the gap between EMIB and Flouros, while also offering some new features. The Foveros Omni can be used as an active bridging chip between two other chips, as an active chip that sits entirely underneath another chip, or as an active chip on top of another chip but overhanging.
The Foveros Omni has never been embedded inside the substrate like EMIB, and it is in any case completely above the substrate. The type of heap causes a problem where the package substrate is not highly connected to the chip located on it. Intel has developed a copper-pillar technology that allows them to transmit signals and power to different z-axis heights and through the chip, so chip designers can have more freedom when designing 3D heterogeneous chips. The Foveros Omni will start with a bump spacing of 36 microns, but will drop to 25 microns in the next generation.
We should note that DRAM also uses advanced 3D packaging. HBM has been using advanced packaging at Samsung, SK Hynix and Micron for many years. These storage cells are fabricated and connected to TSVs, which are exposed and form micro-bumps. Recently, Samsung has even started introducing DDR5 and LPDDR5X stacks, which leverage similar stacking techniques to increase capacity. SK Hynix HBM 3 will hybridly bond 12 vertically stacked chips, each 30 microns thick, with hybrid bonding TSV.
Hybrid bonding is a technique that does not use bumps, and the chips are connected directly through silicon through holes. If we go back to the flip-chip process, there will be no bulge formation, flux, reflow, or areas between the filler chips under the mold. Copper meets copper directly. The actual process is very difficult, and the above section describes this process in detail. In the next part of this series, we'll dive into the tool ecosystem and types of hybrid bonding. Hybrid bonding enables denser integration than any other encapsulation method described earlier.
The most famous hybrid bonding chip is, of course, the recently announced AMD 3D stack cache, which will be released later this year. It utilizes TSMC's SoIC technology. Intel's hybrid keying brand is called Coveros Direct, and Samsung's version is called X-Cube. Global Foundries has unveiled Arm test chips using hybrid bonding. The highest-selling hybrid bonding semiconductor company is not TSMC, and it will not be TSMC this year or even next year. The company that produces the most hybrid bonding chips is actually Sony, which owns CMOS image sensors. In fact, assuming you have a high-end phone, you might have a device in your pocket that contains a hybrid-bonded CMOS image sensor. As mentioned in Part 1, Sony has scaled down the pitch to 6.3 microns, while AMD's V-cache has a pitch of 17 microns.
Currently, Sony is offering 2-stack and 3-stack versions. In the 2 stack, the pixels are at the top of the circuit. In the 3-stack version, pixels are stacked on top of the DRAM buffer cache at the top of the circuit. Progress continues as Sony hopes to separate pixel transistors from circuits and build more advanced cameras out of up to 4 layers of silicon. The picture above shows Sony's sequential stacking with a spacing of 0.7 microns.
Another upcoming high-volume application of hybrid bonding is Xtacking from Yangtze River Storage Technology. Yangtze River Storage uses wafer-to-wafer bonding technology to stack CMOS periphery under the NAND gate. We've detailed the benefits of this technology here, but in short, it allows Yangtze River storage to install more NAND units given the number of NAND layers compared to any other NAND manufacturer including Samsung, SK Hynix, Micron, Kioxia, and Western Digital. The transfiguration is compiled from theemianalysis