Recently, the State Intellectual Property Patent Office disclosed the patent submitted by Huawei in 2019 entitled "Chip Stacking Packaging Structure and Its Packaging Method, And Electronic Equipment".
According to the abstract description, a chip stacking packaging structure (100) and its packaging method, electronic devices (1), involving the field of electronic technology, is used to solve the problem of how to reliably bond multiple sub-chip stacking units (30) on the same main chip stacking unit (10). Chip stacking package structure (100), comprising: a main chip stacking unit (10), having an insulated and spaced multiple main feet located on the first surface (11); the first bonding layer (20), disposed on the first surface; the first bonding layer (20) comprising an insulated and spaced plurality of bonding components (21); multiple bonding components (21) each comprising at least one bonding part (211), any two bonding parts (211) insulation settings, and any two bonding parts (211) The cross-sectional area of the plurality of bonding components (21) is bonded to a plurality of main feet (11), multiple sub-chip stacking units (30), disposed on the surface of the first bonding layer (20) away from the side of the main chip stacking unit (10); the sub-chip stacking unit (30) has an insulated and spaced plurality of microconvexes (31); multiple microconvexes (31) each bonded to one bonding assembly (21).
As we all know, in recent years, because of the limitations of chip shrinkage, the industry has turned to chip packaging to find ways to improve chip performance.
At the recent analyst conference, Wang Tao, managing director of Huawei and director of the ICT Infrastructure Business Management Committee, also pointed out that Huawei is trying to use related technologies for stacking chips, and using less advanced chip processes can also make Huawei's products more competitive. Huawei currently has patent accumulation in chip 3D packaging, and is confident of coming up with more solutions and leading products.
"Huawei has years of accumulation in this aspect, and we are based on chip 3D stacking, 3D packaging or chiplet technology to achieve the most advanced chip or system in the case that the process is relatively not so advanced." Of course, we have accumulated a lot of technology and innovation, so we are confident that we will always provide leading products and solutions to serve our customers and partners. Wang Tao said in a follow-up answer to reporters' questions.
In fact, not long ago, Huawei did disclose another packaging patent.
Interpretation of Huawei's 3D chip stacking patents
Huawei has reportedly developed (and patented) a chip stacking process that promises to be much cheaper than existing chip stacking methods. The technology will help Huawei continue to develop faster chips using older, mature process technologies.
The only question is whether Huawei can really take advantage of its innovations, as foundries can't produce chips for the company without an export license from the U.S. government. But at least Huawei itself certainly believes it can, especially given that the technology could provide performance boosts for chips based on old nodes that aren't so severely restricted by the U.S.
One way to stay competitive
We'll go into more detail about this new technology below, but it's important to understand why Huawei is developing it.
Since the U.S. government blacklisted Huawei and its chip design subsidiary HiSilicon, it now requires all companies that make chips to apply for export licenses because all semiconductor production involves technologies developed in the United States, and Huawei cannot enter any advanced nodes (such as TSMC's N5), so it must rely on mature process technology.
To that end, Guo Ping, former president of Huawei, said that innovative chip packaging and chip interconnect technologies, especially 3D stacking, are a way for companies to invest more transistors in their SoCs and gain the performance they need to be competitive. Therefore, it makes sense for the company to invest in proprietary encapsulation and interconnect methods, such as its patented one.
"Micro and nano technologies, represented by 3D hybrid bonding technology, will become the main means of extending Moore's Law," Guo said.
Huawei executives said that due to the relatively slow progress of modern leading process technology, multi-chip design in 2.5D or 3D package is a common way for chip designers to continuously invest more transistors in products to meet their customers' expectations for new features and performance, which has also become a common way for the industry to adopt. As a result, Huawei's former chairman stressed that Huawei will continue to invest in area enhancement and stacking technologies designed in-house.
Huawei's public statement at the press conference made it clear that the company aims to use its hybrid TSV-free 3D stacking approach (or perhaps a similar and more mainstream approach) for its upcoming products. The main question is whether the method requires any tools or technologies that the U.S. government may consider to be the most advanced and not licensed for export (after all, most fab tools use technology originating in the United States). That said, it remains to be seen whether a foundry will use Huawei's patented method to make 3D chip packages for Huawei. But at least Huawei has a unique inexpensive 3D stacking technology that can help it stay competitive even if it can't use the latest nodes.
No via stacking
Innovative chip packaging and multi-chip interconnect technology will be key to leading processors in the coming years, so all major chip developers and manufacturers now have their own proprietary approach to chip packaging and interconnect.
Chipmakers typically use two packaging and interconnection methods: the 2.5D package enables high-density/high-bandwidth in-package interconnects for small chips adjacent to each other, and the 3D package makes the processor smaller by stacking different chiplets together. However, 3D packages often require fairly complex cabling because the chiplets need to communicate and must be powered using TSV.
Although TSVs have been used in chip manufacturing for more than a decade, they increase the complexity and cost of the packaging process, so Huawei decided to invent an alternative solution that did not use TSVs. Huawei experts designed it to be essentially a hybrid of 2.5D and 3D stacking, as the two small chips overlap each other within the package, saving space, but not completely stacked like the classic 3D package.
Overlapping 3D stacks
Huawei's approach uses overlapping parts of small chips to establish logical interconnects. At the same time, two or more chiplets still have their own power transmission pins, using various methods to connect to their own redistribution layer (RDL). However, while Huawei's patented technology avoids the use of TSV, it is not easy and cheap to implement.
(Image source: Huawei)
Huawei's process involves inverting one of the small chips before connecting to another (or other). It also needs to build at least two redistribution layers to provide power (for example, two small chips mean two RDLs, and three small chips can still use two RDLs, so four, see the patent documentation at the end of the article for details), which is not particularly cheap because it adds several additional process steps. The good news is that the redistribution layer of one of the chips can be used to connect things like memory, saving space.
In fact, Huawei's hybrid 3D stacking approach is arguably more versatile than other companies' traditional 2.5D and 3D packaging technologies. For example, it's difficult to stack two or three power-hungry and hot logic dies together because cooling such a stack would be very complex (which could ultimately mean a compromise on clocks and performance). Huawei's approach increases the surface size of the stack, simplifying cooling. At the same time, the stack is still smaller than the 2.5D package, which is important for mobile applications such as smartphones, laptops, or tablets.
From an industry perspective, other semiconductor contract manufacturers (TSMC, GlobalFoundries), integrated design manufacturers (Intel, Samsung), and even fabless chip-free chip developers (AMD) using leading fab tools and process technologies have also developed their own 2.5D and 3D chip stacking and interconnection methods to serve their customers or their future products. Therefore, Huawei is just following the trend.