The packaging industry is working to expand the adoption of chiplets beyond a few chip suppliers, laying the foundation for next-generation 3D chip design and packaging.
The new chip standard and the cost analysis tool used to determine the feasibility of a given chip-based design are two important new parts. Along with other efforts, their goal is to push the small chip model forward, although there are still challenges and gaps in the technology.
Using this approach, packaging companies can have modular chips or chip "menus" in the library with different functions and process nodes. Chip customers can then select any of these small chips and assemble them in an advanced package, resulting in a new, complex chip design that serves as an alternative to a system-on-chip (SoC).
The chip-cap model has been proven effective by companies such as Intel, AMD, and Marvell, which design their own chiplets and interconnects. Now, other companies in the industry are exploring small chips, largely because scaling has become too difficult and expensive for many, and the power and performance advantages of migrating to new nodes are shrinking. Advanced packaging provides a cost-effective way to combine chips on different technology nodes, while small chips provide a solution that increases the latency of interconnect RC. They also promise to develop complex chips faster and can be customized for specific markets and applications.
Traditionally, to develop complex IC products, vendors have designed a chip that integrates all functions on the same chip. In each subsequent generation, the number of functions per chip increased dramatically. On the latest 7nm and 5nm nodes, cost and complexity are soaring. (A node is a specific process and its design rules.) ）
"The cost of designing new silicon nodes is rising," Mudasir Ahmad, a senior technology development engineer at Google, said in a recent talk. "Just to give you a scale, the cost of making 5nm chips now is about or about the same as the cost of making 10nm and 7nm chips." It is very expensive. ”
While the traditional approach is still an option for new designs, small chips offer customers another solution. But as with any new technology, chiplet integration is not simple. Currently, chip-based designs are used exclusively for high-end products, rather than everyday designs. Even so, building a model based on a small chip requires several parts. Only a few large companies have the required in-house expertise and capabilities, most of which are proprietary.
This limits the adoption of small chip-based approaches to a small number of people. But now, the industry is working to make chip-based designs more accessible. These efforts include:
ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung and TSMC form a new chip alliance. The group has released a new open die-to-die interconnect specification that enables chiplets to communicate with each other in a package. The Open Domain Specific Architecture (ODSA) subproject is putting a final touch on similar technologies. ODSA has also just released a new cost analysis tool that helps determine whether a given chip-based design is feasible. Several packaging companies are developing manufacturing technologies to bring small chip-based designs into production.
Small chips are challenging
Usually, the first step in developing a design based on a chip is to define the product. The proposed chip-based design then requires several parts, such as product architecture, known-good chip (KGD), and chip-to-chip interconnect. It also requires a sound manufacturing strategy.
KGDs are bare dies or chiplets used in designs. Chip-to-chip interconnects allow small chips to communicate with each other in the design. By developing or procuring these parts, chip customers can develop designs based on small chips, at least on paper.
But the biggest question is whether the design is feasible or cost-effective. This could be a major stumbling block that prevents risk-disadvantaged chip customers from considering small chips.
To help customers here, ODSA has released a cost analysis software tool that includes a spreadsheet of all possible components and costs involved in developing a chip-based design.
"There's no general rule that says you should always do small chips, or you shouldn't do it. It all depends on the specific app," said Google's Mudasir Ahmad. "We need a model that we can use for each application to provide feedback. [With the spreadsheet, chip customer] can use a common framework to enter data into it. Then they can try to understand whether it makes sense to make a chip for a specific application. ”
Cost is not the only factor. Engineers must also consider the challenges of small chips. According to Ahmad, here are some of these challenges:
End-of-life costs: If a small chip fails in one or more final designs, the device may be scrapped. This increases scrap costs. Testing: To minimize scrap losses, the design requires more test coverage. Yield: Package complexity can affect overall yield. Performance: Moving signals from one chip to another may degrade the performance of the product.
Business models are another challenge. "If you have different suppliers offering different parts and you put them all in one package, who's responsible for what? Who bears the blame for failure? Ahmad asked.
Architecture, KGD, interconnects
Cost and technical challenges are only part of the small chip equation. Customers must also define products and choose schemas for designs.
There are a lot of options here. Customers can integrate the chip into existing advanced packages or new architectures.
Fan-out is an option. In one example of a fan-out package, DRAM dies are stacked on a logic chip in the package.
For use in high-end systems, 2.5D is another option. In 2.5D, dies are stacked on top of mediation layers, or connected side by side. The intermodal layer contains a through-silicon hole (TSV), which provides an electrical connection from the die to the board. In one example, the ASIC and high-bandwidth memory (HBM) are placed side by side on the mediation layer. HBM is the DRAM memory stack.
Another option is to incorporate the chiplet into the new 3D architecture. For example, Intel is developing a GPU architecture code-named Ponte Vecchio. The device integrates 47 tiles or chiplets with 5 different process nodes in one package.
Figure 1: Different options for high-performance computing packages, based on the mediation layer 2.5D vs. fan-out chip on the substrate (FOCoS). Source: ASE
Figure 2: More examples of 2.5D packages, high-density fan-out (HDFOs), bridged packages, and chiplets. Source: Ann
Any chip-based architecture requires a known-good die, i.e. a die that meets a given specification. Without KGD, the package may experience low yields or fail in the field.
"We receive the die sheets and then put them in packages to deliver a functional product," Lihong Cao, ASE's director of engineering and technical marketing, said at a recent event. "With regard to KGD, we want to fully test it with good functionality. We want it to be 100%. ”
This is not the only challenge. In one package, some dies are stacked, while others are located elsewhere. Therefore, you need a way to connect one die to another using a die-to-die interconnect.
Today's chip designs use proprietary interconnect connectivity chips, which limits the adoption of the technology. "The biggest obstacle to chipping becoming a new IP is standardization," said Richard Otte, president and CEO of Promex, parent company of QP Technologies. "Standard/common communication interfaces must be established between small chips to achieve this across multiple package vendors."
The good news is that several organizations are developing open die-to-die interconnect standards for small chips. There are currently several competing technologies, and it's unclear which one will win or how to combine them.
ODSA is preparing a chip-to-chip interconnect technology called Bunch of Wires (BoW). Other die-to-die technologies include Advanced Interface Bus (AIB), CEI-112G-XSR, and OpenHBI.
In the latest effort, the New Chip Alliance, backed by Intel, Samsung, TSMC and others, has released UCIe, a specification that covers the chip-to-chip I/O physical layer, chip-to-chip protocol, and software stack.
All of the above specifications define standard interconnections between chiplets within a package, but they are all different. "Both UCIe and BoW are open specifications that define the interconnections between chiplets within the package and support an open chip ecosystem. But they're not the same as how you define layers and optimize applications," says Cao of ase.
It turns out that no one interconnect technology can meet all needs. The engineer will select the option that meets the requirements of a given application. "There are areas of overlapping subsets between the various standards," said Choon Lee, chief technology officer at JCET. "So it may not make sense to stick to a standard." Typically, the function blocks of small chips are defined by the device manufacturer. They know how to optimize the interconnection between small chips. ”
Chiplet stacking/binding options
Once the chiplet architecture, KGD, and interconnects are defined, the next step is to determine whether it makes sense to put the product into production.
As before, packages or chip-like designs can be manufactured and assembled at foundries, memory manufacturers, or OSAT. Some (but not all) foundries and memory manufacturers have their own in-house package assembly operations.
Each vendor has different capabilities. Everyone is developing one or more different ways to assemble, stack, and glue different chiplets together. Advanced bonding technologies include hot pressing, laser assisted and copper hybrid bonding.
Both hot press bonding (TCB) and laser-assisted bonding (LAB) use the traditional flip chip process with copper micro-bumps. In this process, copper bumps form on the chip and then use flip chip bonders, LABs, or TCBs to bond the device to another structure. In contrast, copper hybrid bonding uses copper interconnects instead of traditional bumps to stack and connect die.
The traditional flip chip process is used to manufacture multiple package types. A type called ball grid array (BGA) is used in a variety of chip applications.
To manufacture the BGA package, the process first fabricates the chip on the fab's wafers. Then, tiny copper bumps based on the solder material are formed on one side of the wafer. The bump consists of a copper column with a thin nickel diffusion barrier and a tin-silver solder cap.
A copper bump connects one die to another die or substrate in the package. These bumps provide small but fast electrical connections between different structures. Making copper bumps is a well-known process.
Figure 3: Microbump process flow.
Source: John Lau, Unimicron
Once a bump is made on the wafer, the chip is cut. The device then undergoes a traditional flip-chip process.
First, the die is placed in the flip chip bonding machine. Typically, flip chip bonding machines are used to stack and bond dies at bump spacings from 300 μm to 50 μm. Today's bump spacing extends to 40 m and below. (Spacing refers to the space between adjacent bumps on a die.) ）
"Many flip-chip devices don't require fine pitch," says Bob Chylak, chief technology officer at Kulicke & Soffa (K&S). "The flip chip bonding machine removes the chips, dips the solder balls into the flux, and places them on the PCB."
This process is repeated several times. Eventually, several dies are placed on the PCB, sometimes called die substrates. It then undergoes a large-scale reflux process. "The PCB goes through a reflow furnace, where the solder is melted and then cured," Chylak says.
After the reflux process, the die on the PCB undergoes a cleaning step. The system then injects a molding compound into each bump die on the PCB. Wan-Chun Chuang, a researcher at Sun Yat-sen University at The National Sun Yat-sen University, said in a paper: "[This seals] all the components, protects the chips and bumps inside the device." ”
The larger C4 solder ball is then implanted under the base PCB substrate. Finally, the die on the PCB is cut into blocks to create a separate BGA package with a die inside each cell.
The industry needed a different solution to use state-of-the-art copper micro-bumps, including 40μm or tighter pitches. But using a traditional flip chip bonding machine on these pitches is challenging. For finer pitches, some packaging companies use TCBs for chip stacking and bonding applications with 40 μm to 10 μm bump pitches.
Typically, TCBs are used for chip stacking and bonding in 2.5D/3D packages.
Figure 4: 2.5D/3D system architecture. The copper micro-bump connects the intermodal layer to the base die. Source: Rambus
In the TCB process, tiny copper bumps are formed on the die using the traditional bump process. However, in this case, the bumps are smaller and the spacing is smaller. Packaging companies then move away from traditional flip-chip bonding machines and instead use TCB tools.
"Instead of heating the entire board and all the chips on top, the hot-pressing bonding machine grabs the chip, dips it into flux like a normal flip chip, and places it on the PCB," says K&S's Chylak. "There is a heater in the bonding head. This heats to more than the melting point of the solder that holds the chip in place. It then cools down to solidify the solder. ”
At the same time, the lesser-known option LAB is also feasible. In the LAB process, tiny copper bumps are formed on the die using the traditional bump process.
Then, place the bumped die and substrate in the LAB tool. The system uses the heat generated by the laser to align the die and bond to the substrate.
"(Laboratory equipment) has an infrared laser source (980 nm wavelength) and an optical system (homogenizer) that produces a sharp and uniform laser beam capable of selectively heating the target area at a very high heating rate. Wagno Alves Braganca, senior R&D engineer at JCET, said in a paper: Others have also contributed to this work.
In lab systems, the bonding process occurs in less than a second with low thermal stress. LAB is faster than TCB, but it requires specialized equipment from a specific vendor.
Amkor and JCET are developing LABs. The technology has been in production since around 2019. "LAB has been producing high-performance computing applications where non-wet bumps or cracks due to warpage or residual stress can be critical," said Lee of JCET.
OSAT wants to push labs to around 10μm pitch. "We have demonstrated pitches as low as 10 μm using copper lead-free bumps and our laser-assisted bonding method. Our products meet the requirements of the 20μm pitch field. These are chips on wafers, and most of them are specialty sensors," said Michael Kelly, amkor's vice president of advanced package development and integration.
Hybrid bonding
Both TCB and LAB extend to 10μm bump spacing. In addition to this, the industry needs a new solution, namely copper hybrid bonding. Here, the idea is to use fine-pitched copper connections to stack and connect die directly, rather than traditional micro-bumps.
Copper mixing key merge is not fresh. In 2005, Ziptronix introduced a technology called Low Temperature Direct Bond Interconnect (DBI), which is considered the first version of copper hybrid bonding. (In 2015, Tessera acquired Ziptronix.) In 2017, Tessera changed its name to Xperi. ）
In 2015, Sony obtained a DBI license and implemented the technology on its CMOS image sensor production line. Other image sensor vendors are also licensed by DBI.
For CMOS image sensors, the supplier follows a wafer-to-wafer hybrid bonding process. First, two different wafers are processed in one fab. The first wafer consists of a large number of processor dies. The second wafer consists of a large array of pixel array dies.
The goal is to stack each pixel array die on top of each processor die. To do this, insert two wafers into the wafer bonding machine. The bonding machine aligns each chip and connects them using a two-step bonding process. First it forms dielectric-dielectric bonds, then metal-metal connections. Finally, the die on the wafer is cut and encapsulated, forming an image sensor.
Using Xperi's DBI process, Sony and OmniVision are producing CMOS image sensors with 3.1μm and 3.9μm pitches, respectively.
Now, the industry is developing copper hybrid bonding for 3D chip and package applications. AMD, Graphcore, and YMTC have released products from different vendors that use hybrid bonding. Others are working on it.
In packaging, hybrid bonding is used for wafer-to-wafer and chip-to-wafer bonding. In die-to-wafer, two wafers with chips are processed in the fab. The chip on the first wafer is then cleaved and bonded to the second wafer using hybrid bonding.
Figure 5: Xperi's chip-to-wafer hybrid bonding process. Source: Xperi
Chip-to-wafer provides packaging customers with more options, but it is a challenging process. "The CMOS image sensor is formed by wafer-to-wafer hybrid bonding where the bonded chips have a similar footprint and both wafers have sufficiently high yields and mature silicon supply chains and processes," said Abul Nuruzzaman, vice president of product marketing at Xperi. "In 2.5D or 3D advanced packages, chip-to-wafer bonding techniques are sometimes required. It also requires KGD, different die sizes, and dies from different technology nodes or wafer sizes. Cutting, chip handling and assembly must be compatible with hybrid bonding processes, which are relatively new to the industry. ”
In addition to Xperi, Imec, Intel, Leti, Micron, Samsung and TSMC are also developing copper hybrid bonding processes.
All copper hybrid bonding processes are similar. First, the required chip design is processed on both wafers in the fab. Each wafer then undergoes a Damascus process in the fab. For this purpose, the dielectric material is deposited on one side of the wafer. Materially, pattern and etch tiny through holes for each die on the wafer.
The copper material is then deposited on the silicon wafer. The chemical mechanical polishing (CMP) tool then polishes the surface. What remains is copper metallized material in tiny through-holes of each chip. Exposed copper through holes represent pads.
The surface of the wafer must be pristine and free of defects. Therefore, after the CMP, use the metrology tool to check the surface topology for defects. The chip is then cut onto a silicon wafer. Using a wafer bonding machine, stack and bond die onto a second wafer. The final bonding chip is then cut.
It's a challenging process. Unwanted particles and defects may appear on the mold during the flow. Particles can cause holes in the pad. Even if a single 100nm particle falls on a pad, it can cause hundreds of connections to fail.
conclusion
To date, only a handful of vendors have developed and manufactured designs based on small chip sizes. To make the technology more widely adopted, several key pieces are in place.
Given the rising cost of developing chips at advanced nodes, the industry needs small chip models more than ever.
Source: Content compiled by Semiconductor Industry Watch (ID: icbank) from semiengineering, thank you.