Source: ULINK MEDIA (ulinkmedia)
Author: Wheat ear, silversmith
Internet of Things Think Tank reprinted
Guide
On March 2, asE, AMD, ARM, Google Cloud, Intel, Meta (Facebook), Microsoft, Qualcomm, Samsung, TSMC ten industry giants jointly announced the establishment of an industry alliance to jointly create small chip interconnection standards, promote open ecology, and formulate a standard specification "UCIe".
Chiplet "small chip" in 2019 a small fire, when Chiplet in the field of AI chips can be described as a hot word, but the concept has been around for a long time. Chiplet is a silicon-level reuse, is a type of die to meet specific functions, through the pattern of building blocks to make chips, the use of die-to-die internal interconnection technology to package multiple module chips and the underlying base chip together, constitute a multifunctional heterogeneous System in Packages (SiPs) chip mode, to establish a Chiplet chip network.
This is also considered an important solution to continue the "dead" of Moore's Law.
In 2019, AMD proposed to break the limitations of Moore's Law, and the revolutionary Infinity Fabric (a dedicated channel for two 4-core CPUs interconnected) set off a small chip trend. At that time, most of the limitations on this technology would mention interconnection standards and packaging technology.
The full name of the UCIe standard is "Universal Chiplet Interconnect Express" (Universal Chiplet Interconnect Channel), which establishes a unified standard of interconnection at the chip package level, providing high-bandwidth, low-latency, energy-efficient and cost-effective package connections between chiplets.
The UCIe 1.0 standard defines the inter-chip I/O physical layer, inter-chip protocol, software stack, etc., and utilizes two mature high-speed interconnection standards of PCIe and CXL. This standard was originally proposed and formulated by Intel, and then opened to the industry and jointly formulated.
It addresses connectivity to compute, memory, storage, and entire computing continuums across the cloud, edge, enterprise, 5G, automotive, performance computing, and holding domains. UCIe offers the ability to package cores from different sources, including different fabs, different designs, and different packaging technologies. This wave directly hits the chip semiconductor industry, but the vertical market it covers is also immeasurable.
Why Chiplet Package Integration?
Let's start by distinguishing between SOC, SIP, and Chiplet.
SOC (system on chip) System-on-chip. It is the chip integration of the core of the information system, which integrates the key components of the system on a chip, like a micro-small system. In the PC era we can say that the core of a computer is the CPU, and in the era of smart terminals, the core of the mobile phone is soC. It still follows the direction of Moore's Law.
SOC simulation schematic, source network
SIP (System-in Package) system-in-package. SIP package does not have a certain form, the use of simple wire combination or overmolding, the processor, memory, FPGA and other functional chips in a 2D or 3D package structure integrated in a package, can be customized production. SIP goes beyond the direction of Moore's Law, and the more integrated in SIP is Bluetooth and 802.11 (b/g/a), mostly used in solutions covering communication technologies, while UWB is another ideal application for SIP.
Chiplet is the core grain, also known as the chiplet. It is actually a plurality of core particles formed through advanced packaging technology SIP, the different process nodes and different materials of chips through advanced integration technology (such as 3D integration technology) package integration together, the formation of a system chip, to achieve a new form of IP multiplexing. It got rid of the direction of Moore's Law.
UCIe supports open Chiplet-state systems that deliver platforms on packages
Moore's Law, which has been developed for more than 50 years, has reached its limit, and now the demand of the industry is becoming more and more difficult and costly for the traditional single process and single chip, and it is urgent to change. Core package integration enables a fast and cost-effective way to provide a custom solution, for example, different paths may require the same acceleration capabilities, but the same core, memory, and I/O. Now, it also allows core co-packaging based on the best process node selection based on function, and the inter-chip inter-chip interconnection through UCIe can greatly reduce manufacturing costs.
The data shows that the design cost of 10nm chips is 174.4 million US dollars, 7nm chips have soared to 297.8 million US dollars, and 5nm chips are as high as 542.2 million US dollars, and even industry giants are increasingly struggling. The new UCIe standard specification makes it possible for small chip interconnection from different manufacturers, and x86, ARM, and RISC-V are integrated together.
UCIe 1.0 defines two types of encapsulation: physical layers and communication protocols. First, package-level integration, connected to the board-level components, such as memory, accelerators, network devices, modems, etc., can be integrated at the package level, suitable for holding to the end server, through the same package options to connect to multiple sources of core. The second is to enable different types of media (e.g., cables, milliwave) to provide out-of-package connection retimers to transmit the underlying protocol at the rack very pod level to achieve resource pooling, resource sharing, and good energy efficiency and cost-effective performance at the edge and in data.
Why Chiplet is needed in the era of the Internet of Things
The biggest dilemma of the Internet of Things is that it is seriously fragmented, including technology fragmentation and application fragmentation.
Different application scenarios require different IoT technology capabilities, such as communication technology common 4G, 5G, NB-IoT, Cat.1, LoRa, wifi, Bluetooth, zigbee and other proprietary protocols.
In some scenarios, 4G+ Bluetooth needs to be used, and some scenarios require Cat.1+ wifi or Cat.1+ wifi + Bluetooth and other differentiated needs.
Of course, in addition to communication chips, there are more commonly used IC devices in IoT devices, such as different types of MCUs, capacitors, inductors, memory, PA, and hundreds of millions of sensor categories.
The fragmented IoT market is destined not to be a general IC that can be used, because a powerful IC can of course cover many application scenarios, just like using a 5G SoC for smart water meters, of course, it can also be used, but this belongs to the "chicken killing with a cattle knife", which not only wastes most of the capabilities of 5G, but also very expensive, not a market-oriented behavior.
The choice of technical solutions in the market will eventually be implemented to the cost performance, and the extremely fragmented IoT application market needs to be customized according to the needs of the corresponding most cost-effective solutions.
The general solution does not work, and chiplet provides the idea of integrating small chips with different functions together, so that the chip's ability can be like a stacking wood, stacking out the functions they want, which has become an inevitable choice for the industry.
A bright future
With the continuous increase in the demand for intelligence in vertical fields, the demand for processors for various heterogeneous applications such as graphics processing, security engines, artificial intelligence (AI) integration, and low-power IoT controllers, market research firm Omdia has estimated that the global Chiplet serviceable market size will increase to $57 billion in 2035. The opening of the UCle standard will greatly increase this value and play a greater value in communications, industry and other fields.
The first is the flexibility of the architecture design, where the interconnect of silicon allows for huge improvements in bandwidth, latency, and power consumption. The second is the diversity of business models, due to the collection of multiple modules, which broadens the choice of supply chains and vertical fields, and can tap into more potential markets.
However, Chiplet still has many challenges, based on the current international situation and the actual development level of the domestic industry, the difficulties to be faced in China are not the same as those of international head IC design companies. Domestic manufacturers are also already promoting Chiplet technology, such as Huawei HiSilicon, ZTE, etc. have achieved a certain degree of mass production, but the OEM is still completed by TSMC. Domestic manufacturers to take the "self-research" route, still need to polish for a long time.
Resources:
Fast technology: AMD, ARM, Intel, Qualcomm, Samsung, TSMC and other ten giants together! Create a small chip interoperability specification
Ic's Sail Brother: The difference between IP, SoC, SiP and Chiplet
Semiconductor industry observation: What kind of development route should Chiplet, which continues Moore's Law, take?