There are still many mysteries about Apple's self-developed chip M1 series.
Just recently, about the follow-up of M1 chip, M2, M3 rumors have come, but mostly some wind-catching information, for architecture, performance, core these are not particularly clear information, but more around the TSMC process node upgrade.
M1 is not finished, M2, M3 may be coming. Image courtesy of Progamer
TSMC's new process processes such as 4nm and 3nm may be a large upgrade point. In this way, the M1 series, which has amazed everyone in terms of energy consumption ratio, M2 and M3 have only increased.
But, two years later, what about when the node process is upgraded to 3nm?
There are probably two, one is to dry the node process to 1nm, wireless approaching the physical limit, but it is more difficult. The other is to bypass the benefits brought by the node process upgrade and take the chiplet "small chip" road.
Not enough for one M1 Max? Then load the Mac Pro with two
However, Apple, which has always disliked being manipulated by the supply chain, may also be looking for a feasible way to eat nodes and arm chips while having the advantage of high energy efficiency ratio.
From M1 to the more powerful M1 Pro and M1 Max, they have almost the same architecture, and the performance release of single cores is relatively close, and the biggest difference is actually in the number of cores.
Even, you can simply understand that ARM-based M chips rely on the number of heap cores to achieve a higher performance ceiling.
M1: CPU 4+4 core, GPU 8 core, 16 billion transistors, 16 core neural network;
M1 Pro: CPU 2+8 core, GPU 16 core, 33.7 billion transistors, 16 core neural network;
M1 Max: CPU 2+8 core, GPU 32 core; 57 billion transistors, 16 core neural networks;
From a simple perspective from another dimension, the M1 chip area is about 120mm, the M1 Pro is 245mm, and when it comes to M1 Max, it directly soars to M1 Max 432mm.
The same generation of M chips, the more Max, the number of cores, chip area is about Max, from here it is not difficult to understand Apple's naming rules for M chips, easy to understand, Microsoft, Intel, Qualcomm really should learn well.
Although Tim Millet, Apple's chip architect and vice president, elaborated on Apple's journey to develop M chips in the Upgrade podcast as early as November, he did not say anything about how the M chip will develop next and how to make Max more on top of Max.
Tim Millet, Apple chip architect and vice president. Image courtesy of Apple
With the MacBook Pro 14/16 successively launched, after many folk DIYer explorations, it seems that Apple has also found that Apple has made M1 Max more Max.
It's "put two M1 Maxes in there and even double them."
M1 Max hides the area. Image credit: HothardWare
This conjecture is actually based on the dismantling, found that M1 Max has an extra "unknown area" relative to M1 Pro, after a brain hole, the guess is to connect two or even more M1 Max reserved "high-speed bus".
Tim Cook：Intel，this is for you. 图片来自：Max Tech
This also fits the rumors that the new iMac Pro and Mac Pro will use multiple M1 Max processors. "It's like playing with Lego, building blocks, punching the teacher to death."
However, the term "building blocks" is not very accurate, and the "puzzle" is more accurate. In this way, the chip area of the double M1 Max will be considerable, and four times that is even more unprecedented.
The M1 Max Duo is almost certain over Nvidia's top GPU, the GA100 chip area (826mm).
Such a huge SoC, throughout the history of semiconductors, can definitely be counted as a "T-Rex" level chip, not to mention that it will be based on the 5nm process, and the cost is likely to exceed any contemporary chip.
When the M series chip walks into "Jurassic Park"
From the original ENIAC, which weighs 30 tons and covers an area of 170 square meters, to today's desktop PCs, the equipment is almost all developing towards miniaturization and integration.
The same is true of processors in the semiconductor world, when the process node is still in μm, Intel's original Pentium area is about 294mm, based on the 0.8μm process.
Intel Pentium III Xeon.
In the x86 processor era, the Intel Pentium III Xeon has an area of 385mm and is based on a 0.18μm process. However, at that time, many processor manufacturers were strictly controlling the volume and suppressing the cost of introducing more affordable PCs to the public.
Subsequently, whether it is the popularity of 64-bit or the leap of process nodes, the size of the processor is mostly controlled below 500mm, cost control, and the efficient use of wafers, which almost curbs the development of consumer-grade processors for "dinosaurization".
The consumer semiconductor industry also seems to be gradually moving from Jurassic to a new era.
Folk gods are also making suggestions for the development of Apple's M chip. Image credit: Twitter
At this time, the possible development route of Apple's M chip seems to be back to "Jurassic", but the processor size jumps at the same time, and the density of transistors does not fall.
Although it sounds like putting two chips together, it should not be difficult, and there is no need to redesign the architecture and core. But in practice, as the chip area increases (especially by doubling), and with sufficient yield and capacity, the cost takes off directly.
Apple's M series chips are still a consumer-grade product, a year ago to get rid of Intel, on the one hand, in order to control the product force, on the other hand, in fact, to control the cost, to maximize profits. The erratic cost of a large-area SoC is clearly not what Apple expected.
M1 Max's highest unified memory is 64GB, so M1 Max Duo goes straight to 128GB?
On the other hand, the design of two or more M1 Max splices, Unified Memory (UMA), will also be a huge challenge, and it is inevitable to re-plan the location of multiple cores, introduce more bandwidth, and higher capacity memory.
For the public, it may be more complex chip design, and for private, it may invisibly increase the cost by several times, which will be the two major stumbling blocks for Apple's M chip to become Max.
Moore's Law is in the past, and the sun arch is the present
"The number of transistors that can be accommodated on an integrated circuit will double approximately every two years." This is the famous Moore's Law, which also has another saying, "Every 18 months, the performance of the chip doubles."
MacBook Pro 16. Image courtesy of: dpreview
The performance here actually refers to the number of transistors, and the M1 Max has a 3.5 times performance improvement compared to M1, which also reflects the gap in the number of transistors.
Doubling the number of transistors here in the M1 series is an increase in chip area. Historically, it is more dependent on technological progress, from μm to nm, and the number of transistors has jumped from millions to hundreds of millions.
But around 2013, Moore's Law slowed down, and from then on to the present, the benefits of improving process nodes for performance are decreasing.
More advanced processes can indeed turn up the number of transistors, but they are also accompanied by changes in cost and yield.
TSMC expects to start production of the 3nm process in 2023. Image courtesy of Anandtech
According to data published by the International Business Strategy Corporation (IBS), the design of the 3nm chip is expected to cost $590 million, while the 5nm is only $416 million, the 7nm is $217 million, and the 28nm is only $40 million.
TSMC previously announced that it will invest $20 billion to build a 3nm wafer factory, also for 3nm, and Samsung consumes no less than TSMC.
So far, only TSMC and Samsung are actively laying out 3nm wafers, and other manufacturers are not unwilling, but they can't afford to spend this money.
On the other hand, the yield rate of the chip decreases with the increase of the area, and the design pass rate of 700mm is only about 30%, and the yield rate of 150mm soars to 80%.
In any case, the road to chip upgrade seems to have been blocked.
AMD's ZEN 2-based EPYC 2 (Rome) processor. Image credit: AMD
In order to continue to increase the scale and density of chips, many people have shifted their attention from the upgrading of process nodes to the packaging process, which is AMD's chiplet (chiplet) technology.
Chiplet is simply like dumplings stuffed with tangyuan filling, packaging small chips with different functions together, rather than cutting directly from the wafer, and using advanced packaging processes to compensate for the stagnation of process nodes.
The most vivid metaphor for Chiplet at the moment (but I don't approve of this way of eating).
In recent years, AMD has continuously increased the processor density through Chiplet technology to counterattack Intel and gradually began to seize the market.
For chiplets that have risen in recent years, The Linley Group, an authoritative consulting organization in the technology industry, directly proposed in the article "Why Big Chips Are Getting Small" that Chiplets can reduce the design cost of large 7nm chips by more than 25%, and the cost savings will be higher when facing 5nm and higher processes.
AMD 3D Chiplet-based package of Ryzen 9 5900X CPU.
The 3D V-Cache announced by AMD is also confirming that the Chiplet combined with the old process and the advanced packaging process can achieve higher node performance, and even mix the chips of different process nodes, which has enough flexibility.
In addition to reducing costs and achieving more advanced performance, Chiplet will also speed up the time to market, after all, the use of old chips directly with advanced packaging processes can be used, and even the layout of advanced process nodes can be completely ignored.
Having said all the benefits, Chiplet also has corresponding disadvantages, the stacking of small chip 2D, 3D has a very high demand for thermal management design, and the total thermal power consumption in the package will be significantly improved.
Chiplet-based Intel server chips. Image courtesy of nextplatorm
But in any case, Chiplet has been recognized by many institutions and manufacturers as an important technology for continuous breakthroughs in chip performance in the post-Moore era.
M1 inside Mac mini with MacBook Air.
Back to the original Apple's self-developed M chip, through the ARM architecture, and the upgrade of process nodes, the energy efficiency ratio is continuously improved, and the yield and cost are controlled by the way. As for whether it will be spliced together by multiple M1 Max to form a complex giant SoC into the workstation-level Mac Pro, for now, Apple has enough capital and strength to design and produce a processor similar to the "prehistoric behemoth".
Unofficial rendering of iMac Pro 2022.
As for Chiplet, I think it must have appeared on the drawings of Apple's chip team, rather than facing the future of unclear process node improvement, it is better to take the initiative to change, with the current M chip, A chip to complete a deeper SoC upgrade.
The possible M1 Max Duo is also very likely to become the largest SoC in apple's core history, and there is no one to come.
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