In the history of computer development, the improvement of computer performance mainly relies on the progress of the processor it carries, such as from Pentium (Pentium) to Core, from bulldozer (AMD FX) to Zen, and the improvement of chip performance depends on the progress of chip technology, such as the mainstream way adopted by the chip industry is to improve the advanced process of the chip to improve its performance, so that the chip process from 14nm to 5nm continues to shrink, the same size of the chip into more transistors to enhance its computing power.
Apple, Nvidia has always been the pursuit of advanced processes, the two manufacturers' computing power products are entrusted to the wafer foundry TSMC FOUNDRY, and strive for the production capacity of its advanced processes, closely follow the latest technology in the chip industry, it can be said that the two latest releases of products bring together the current process level and technical capabilities of the chip industry, from the recent Apple and Nvidia press conference revealed product information can find a surprising fact - the strongest performance of the surface of the processor chip are using the "assembly" process.
Disrupt the industry's "assembled" chips
The first bombshell was dropped by Apple.
When the market expects to be accustomed to the same chip process and the processor performance increases by between 10% and 20%, Apple's self-developed computer chip M1 Ultra, which also uses TSMC's 5nm chip process, has far exceeded the hardware performance indicators of the M1 Max released only half a year ago. At that time, the market was also shocked that the M1 Max's chip area was 432 square millimeters, which was the size of nearly 4 M1 chips, and M1 Ultra doubled the size of the chip on this basis.
The increase in chip size means that it has more transistors, the M1 Ultra has a total of 114 billion transistors, while the number of transistors released by M1 Max half a year ago is 57 billion, followed by a doubling of the number of CPU cores, GPU cores, and neural network engines. The M1 Ultra supports 20 CPU cores, 64 GPU cores, and a 32-core neural network engine with a bandwidth of 128GB and up to 22 trillion operations per second.
Looking closely, it is not difficult to find that the core data of the M1 Ultra is basically double the previous generation of M1 Max, M1 Ultra seems to be the two M1 Max "glued" together, and it is true that M1 Ultra is through a packaging technology called UltraFusion, the two M1 Max are combined into one, through this packaging technology, Apple has achieved a data transmission speed of 2.5TB/s between the two chips.
Johny Srouji, senior vice president of hardware technology at Apple, said: "By connecting the two M1 Maxes with our UltraFusion package architecture, we were able to expand Apple's chip materials to new heights like never before." "With its powerful CPU, massive GPU, incredible neural engine, ProRes hardware acceleration, and massive amounts of unified memory, the M1 Ultra makes the M1 family the most powerful PC chip in the world."
Immediately afterward, Nvidia dropped another "nuclear bomb" two weeks later.
At NVIDIA's annual GTC conference on March 22, Jen-Hsun Huang unveiled its dedicated data center CPU, Grace CPU Superchip, which he calls "the ideal CPU for ai factories." Grace CPU Superchip is based on armv9 architecture, has 144 Arm CPU cores, its memory bandwidth reached 1TB/s, according to SPECrate2017_int_base benchmark data, Grace CPU Superchip's analog performance score reached 740, which is 1.5 times (460 points) of the DGX A100.
Amazingly, this super chip is also "glued" together by two chips, Grace CPU Superchip is composed of two Grace CPUs, through the chip interconnect technology NVIDIA NVLink-C2C to connect the two Grace CPUs together, in fact, as early as last year, Nvidia released grace Hopper Superchip used this technology to connect the chip.
It is not difficult to find that from Apple M1 Ultra to NVIDIA Grace CPU Superchip, it is a mechanism to "assemble" two identical small chips together to achieve performance, does this mean that the future is a big cost to slowly develop 2nm, 1nm advanced process is not worth the loss, just need to continue to push the chip to achieve performance double? So why did this chip "assembly" technology fail to become the mainstream of the industry before that?
This actually involves chiplet, a packaging technology that has been very hot in the semiconductor industry in recent years.
The sole leader "sealed" the Chiplet
Whether it is the UltraFusion package architecture used by Apple's M1 Ultra or the chip interconnect technology NVIDIA NVLink-C2C used by NVIDIA, there are interconnections between related chiplets. Ian Buck, vice president of hyperscale computing at NVIDIA, has said: "In order to cope with the slowdown in the development of Moore's Law, small chips and heterogeneous computing must be developed. ”
The chip in Ian Buck's mouth is the chiplet, which is often translated as a core grain. It is the chip of IP modules in the system-on-chip (SoC), and chiplet technology can improve yield and reduce costs, while improving design flexibility and shortening the design cycle.
The current system-on-chip (SoC) is not just a CPU or a GPU, but CPU, GPU, ISP, NPU and other computing units are on a chip, in simple terms, chiplet technology can be imagined as a Lego building block, chiplet is to modularize these different computing units, multiple chiplet modules can be spliced into a system-level chip (SoC), and in the past, a system-level chip (SoC) can not be cut again. The advantage of this is that a complete wafer can be split into more chiplets, which means lower cost consumption at the same yield.
For example, when a wafer is cut into a package, there is a point of damage, directly made into a system-on-chip (SoC) can be cut into 10 pieces, if the chiplet is made into 100 pieces, then the yield of the wafer into a system-level chip (SoC) is 90%, and the yield rate of the chiplet can reach 99%.
Chiplet in addition to greatly improving the yield of large chips, reducing design costs and other economic benefits, chiplet technology also provides a possibility for heterogeneous chip manufacturing, this modular chip can achieve different architectures, different materials, different process nodes and even different wafer foundry products integrated into a chip, thereby quickly generating a super chip that adapts to different functional needs.
For example, several generations of AMD products have adopted the "SiP + chiplet" heterogeneous system integration model, and at the same time, at the GTC in March this year, Nvidia in addition to releasing grace CPU Superchip, also launched Grace Hopper Superchip, which is not composed of two identical Grace CPUs, but consists of a Grace CPU and a Hopper architecture GPU. These are all the process possibilities that Chiplet provides for the design and production of super chips.
Some people think that the advanced packaging technology represented by chiplet is becoming the key to surpassing Moore, and Gordon Moore made a prediction in the semiconductor field based on his own experience: "Under the premise of minimum cost, the number of components contained in integrated circuits can be doubled about every year." （The complexity for minimum component costs has increased at a rate of roughly a factor of two per year)
Now, 57 years after Moore's Law was proposed, it is becoming increasingly difficult to make more transistors and smaller processes on thumb-sized chips. Technically speaking, as the chip size shrinks, the serious problems of leakage, heat generation and power consumption caused by the short-channel groove effect have been plaguing the chip process continue to shrink. When the material approaches the physical limit of 1nm, the quantum tunneling effect causes a certain number of electrons to cross the barrier and thus leak electricity, which is a problem that is temporarily insoluble for humans.
Although Moore's Law is still struggling to maintain, but the industry does realize that the process will not be infinitely reduced, transistors can not be infinitely increased, it can be said that the industry will be advanced packaging technology to the same degree as the process of microdirection, from wafer foundries to packaging and testing manufacturers are increasing investment in advanced packaging technology, since last year, advanced packaging technology has become a major fab, packaging and testing manufacturers and even some Fabless key investment areas.
As early as January 2021, TSMC President Wei Zhejia revealed at the earnings conference: "For advanced packaging technologies including SoIC, CoWoS (the process used in Apple M1 Ultra), we observed that chiplet is becoming an industry trend. TSMC is working with several customers to develop 3D packages using the chiplet architecture. ”
In June, the packaging and testing leader Sun Moonlight announced that it would invest $2 billion to improve its wafer packaging business; in July, Intel announced a roadmap for future process processes and packaging technologies, which will continue to promote the application of Coveros 3D stacking packaging technology and EMIB (embedded multi-tube interconnect bridge) packaging technology; in September, UMC and packaging and testing manufacturer Jibang exchanged shares.
Under the boom of additional investment by major semiconductor manufacturers, the chiplet market has also ushered in rapid development. According to Omdia, chiplet's market size will reach $5.8 billion in 2024 and more than $57 billion by 2035, and the market size will usher in rapid growth.
Of course, the implementation of chiplet requires the integration of many technical interfaces, as mentioned above, chiplet can achieve different architectures, different materials, different process nodes and even different wafer foundry products integrated into a chip, but different chip manufacturers use different connection protocols, such as NVIDIA Grace CPU Superchip using NVLink-C2C technology, Apple M1 Ultra using TSMC to provide the connection protocol, Intel also has its own licensing agreement, AIB.
There is no doubt that the chip giants are creating a product ecology and seizing the market through their own chiplet protocols, but the emergence of chiplet technology is originally intended to break the barriers between different ecosystems, and if it causes the fragmentation of the industrial chain due to the connection agreement behind it, it can be said that it is not worth the loss, so at the beginning of March this year, the semiconductor industry's first chiplet interconnection interface standardization "bridge" - UCIe Alliance became.
Is UCIe an opportunity or a flood beast?
On March 2 this year, Intel, AMD, ARM, Qualcomm, Samsung, TSMC, Sun Moonlight and other semiconductor industry chain manufacturers, as well as Google Cloud, Meta, Microsoft and other Internet hardware terminal companies announced a new technology standard UCIe (Universal Chiplet Interconnect Express).
In simple terms, UCIe is an open industry interconnection standard, which defines the interconnection standard between small chips, which means that the semiconductor industry is creating a standardized, generalized, plug-and-play chiplet interface, and the promotion of this open standard will undoubtedly bring the entire industry a huge space for innovation, which not only has the advantages of high bandwidth, low latency, economic and energy saving, but also can be applied to all fields including computers, cloud edges, 5G, automobiles and mobile devices.
However, although the industry interconnection standards formulated by UCIe are good, it is not difficult for sharp-eyed people to find that none of the top ten companies that founded the alliance are from China, especially in such an extremely sensitive industry as semiconductors, does this mean that the UCIe industry alliance wants to develop a protocol to establish its own rules of the game in the chiplet process, so what is the cost for new players to join? Is it to pay a licensing fee like Arm, or can it be used as a "card neck" tool?
For domestic chip companies, the advanced packaging represented by chiplet technology is now a high-quality track suitable for long-term investment, after all, in the short term, domestic companies cannot obtain EUV lithography machines through self-research or import. Although, now we are in the era of lithography to drive size reduction, but the future drive chip industry may continue to move forward may be the stage of collaborative optimization of design and process, as well as the stage of collaborative optimization of system and process, then, advanced packaging or the beginning of the next chip industry reshuffle, chiplet has become an excellent technical opportunity for the continental chip industry to overtake in the bend, but now, the UCIe industry alliance has been established one step ahead, will it become another mountain blocked in the future?
The good news is that the mainland's chiplet industry interconnection standard system is also in full swing, since March 28 this year, the China Computer Interconnection Technology Alliance (CCITA) joint electronic standards institute, the Chinese Academy of Sciences Institute of Computing, the Ministry of Industry and Information Technology and a number of domestic chip manufacturers have completed the "small chip interface bus technology", "microelectronic chip optical interconnect interface technology" draft standard formulation, domestic related enterprises involved in small chip technology can feedback draft opinions through CCITA and the alliance.
It should be noted that there are no small differences between the "small chip interface bus technology" of the China Computer Interconnection Technology Alliance and the relevant standards formulated by the UCIe Alliance, such as the CoWoS (process used by Apple M1 Ultra) technology, which TSMC is proud of, which cannot be achieved by the mainland packaging and testing plants. To put it simply, "Small Chip Interface Bus Technology" is suitable for the current situation of China's chip industry chain, biased towards mature processes, and the relevant standards of the UCIe Alliance pay more attention to the performance of chiplets in advanced processes to some extent.
Of course, this does not mean that "Small Chip Interface Bus Technology" is not as good as UCIe, and when SMIC, Huahong Semiconductor and other top fabs in mainland China cannot manufacture advanced process chips, exploring small chip interconnection technology that is more suitable for the current industrial chain situation is down-to-earth. Hao Qinfen, secretary general of the China Computer Interconnection Technology Alliance and researcher at the Institute of Computing of the Chinese Academy of Sciences, believes that the domestic chiplet standard can be made in a more mature and low-cost way, which can replace the expensive scheme of advanced processes.
Just when many people think that there is no hope for Chinese chip companies to join the UCIe Alliance in the future, and china's semiconductor industry has to take another hard move, Intel, the initiator of the establishment of the UCIe Alliance, actually pulled a mainland chip company, ChipWing Microelectronics, into the UCIe Alliance on April 2.
Where is the veriSilicon microelectronics? According to the company's official website, VeriSilicon is a domestic semiconductor IP supplier, with graphics processor IP, neural network processor IP, video processor IP, digital signal processor IP, image signal processor IP and display processor IP six categories of processor IP core. According to the statistics of the research institute IPnest, VeriSilicon is the first Chinese mainland and the seventh highest semiconductor IP supplier in the world, and at present, VeriSilicon has launched a processor platform based on the Chiplet architecture, and the 12nm SoC version of the platform has completed tape-out and validation, and is iterating the chiplet version.
What the core enterprises of China's semiconductor IP mean by joining the UCle Alliance are still difficult to say, whether it is good or bad still needs time to verify, but no one dares to guarantee that UCIe will be completely open to Chinese chip companies, after all, there is a lesson from the past, this is not a simple choice of Lightning interface or Type-C interface problem, the technical route represented behind it, the industrial chain that supports it and even the economic game behind it can not be underestimated.
The only thing that can be determined is that the "small chip interface bus technology" and "microelectronic chip optical interconnection port technology" that have completed the draft in China cannot stop and bring together more enterprises as soon as possible, so that the landing and continuous iteration of domestic chiplet technology labeling is a difficult but certain thing to do.
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