4nm chip reproduces the power consumption problem, how advanced process chips can crack the leakage "curse"

Recently, a number of mobile phones using 4nm process chips have been complained by users that there are problems such as high heat generation and high power consumption. It is understood that the three top mobile phone chips suspected of overheating power this time are Qualcomm Snapdragon 8 Gen 1, Samsung Exynos 2200, and MediaTek Tianji 9000, all of which are representatives of high-end chips of various manufacturers. Meanwhile, the producer of the Tianji 9000 is TSMC, exynos 2200 and Snapdragon 8 Gen 1 producer Samsung, the top two chip foundry manufacturers.

At the beginning of last year, the 5nm chip was frequently complained about due to the heat problem, and now the 4nm chip is once again in the same dilemma: the advanced process chip has leakage current problems, resulting in excessive heat generation, which seems to have become a "magic spell" and is one of the biggest obstacles to the chip process process. The process of chip is still extending, and how to effectively crack the leakage "spell" in the future has become the direction of efforts in the entire chip manufacturing field.

Challenges posed by the short channel effect

In general, according to The Denner's scaling law, as the chip size shrinks, the required voltage and current will also decrease, because the power consumption will be affected by voltage and current, when the process process is improved, the voltage and current will decrease, and the power consumption generated by the chip will also decrease. TSMC said that compared with the 7nm process, the power consumption of the 5nm process is reduced by 30% under the same performance, and the performance is improved by 15% under the same power consumption.

However, as the chip process enters 5nm, the problem of excessive power consumption is frequent. Zhao Chao, executive vice president of Beijing Superstring Memory Research Institute and part-time doctoral supervisor of Beijing University of Aeronautics and Astronautics, believes that the short channel effect is one of the main reasons for the power consumption problem of advanced processes such as 4nm and 5nm, and has also become the biggest obstacle to the development of advanced processes.

In semiconductor manufacturing, the size of integrated circuits continues to shrink with the development of Moore's Law, and the length of the channel is correspondingly shortened, which leads to the shorter and shorter distances of S and D (source and leakage) in the channel pipe. Therefore, the control ability of the gate to the channel becomes worse, which means that the difficulty of the gate voltage clamping the channel becomes greater, that is, the short channel effect is generated, resulting in a serious current leakage (leakage) phenomenon, and finally the heating and power consumption of the chip are out of control.

"The 5nm and 4nm chips use FinFET (fin field effect transistor) structures. FinFET structure after the chip process into 28nm, compared with the planar MOSFET device structure, has a stronger gate control capability, FinFET structure can increase the contact area between the gate and the channel, to enhance the control of the conductive channel. The increase in the contact area of the channel can alleviate the short channel effect to a certain extent, thereby extending the chip process. However, as the chip process gradually extends to 5nm and below, chips that use advanced processes of FinFET structure also have short-channel benefits caused by leakage. This is also related to the structure of the FinFET itself. FinFETs use a three-sided grid structure, not a four-sided surround structure, in which one direction is not wrapped in a gate. With the continuous reduction of the chip process, the control ability of the FinFET three-sided gate structure for leakage is gradually weakening, causing the chip to have power consumption problems again. Zhao Chao said.

How to crack the "curse" of leakage?

In the future, the chip process will continue to extend to 3nm or even 2nm, and people are also actively considering how to solve the power consumption and heat generation problems caused by leakage current, including replacing new materials and adopting new architectures - GAA (surround gate) structure, in order to break the long-standing leakage "curse".

In terms of materials, Zhao Chao introduced that the use of gate dielectric materials with high dielectric constants instead of the original silica materials can effectively solve the problem of gate leakage caused by short channel effects. Hafnium dioxide belongs to the high dielectric constant of the material, with hafnium dioxide to replace silica as a gate dielectric material, can effectively improve the dielectric constant, reduce leakage, and effectively increase the capacity of capacitance charge.

At the same time, with the extension of the chip process, the GAA technology using a four-sided ring grid structure has gradually attracted more attention. Zhou Peng, deputy dean of the School of Microelectronics of Fudan University, said that compared with the FinFET structure of the three-sided fence, the four-sided ring gate structure of GAA technology can better inhibit the formation of leakage current and increase the drive current, which is more conducive to achieving an effective balance between performance and power consumption. Therefore, GAA technology is more widely recognized and favored by the industry in the smaller process after 5nm.

However, whether it is a new material or a GAA technology, it is difficult to solve the problem in a short period of time. Researchers have found that if you want to use hafnium dioxide in carbon nanotube transistors to replace silicon dioxide as a gate dielectric material, hafnium dioxide is also difficult to form a high dielectric constant dielectric in the required thin layer.

Mass production of GAA structures is equally difficult. It is understood that the recent Samsung uses GAA structure to build a 3nm chip, the yield is only between 10% and 20%. TSMC will continue to use the FinFET process in its first-generation 3nm process.

"In the field of semiconductors, the conversion or change of any technology often needs to go through years of trial and error and improvement, although the GAA structure has obvious advantages in the process below 5nm, but whether it can ultimately achieve the expected high performance and low power consumption also depends on whether the technical problems faced in the process can be overcome one by one." Zhou Peng said.

4nm is not a gimmick

For the power consumption problem of the 4nm chip, some consumers also questioned whether 4nm is just a commercial gimmick. 4nm and 5nm technology is actually not much different, otherwise why is the problem of high power consumption and high heat generation still the same?

In general, the name number of the chip process is evolved at a rhythm of 0.7 times, for example, after the 14nm process, the complete process iteration should be 10nm (14nm x0.7≈10nm), 7nm after 10nm, and 5nm after 7nm. If this rule is followed, it seems unclear whether it should be 4nm or 3nm after 5nm. However, under the convention of the foundry, the complete process iteration of 5nm should be 3nm. Therefore, 4nm should belong to the transition process of 5nm and 3nm, and its role positioning is similar to the previously launched 8nm (transition process of 10nm and 7nm) and 6nm (transition process of 7nm and 5nm). In the case of the delay of the 3nm process in each foundry, the value of 4nm seems to be to fill the market gap in this time.

However, this does not mean that the 4nm process is equivalent to 5nm. Although the 4nm process does not belong to the "complete iteration" of the 5nm process, it is also a "same-generation evolution". TSMC has promised that its latest 4nm process will improve performance by 11% and energy efficiency by 22% compared to 5nm.

In this regard, experts explain that there are many factors that cause power consumption problems in 4nm process chips, and it is difficult to generalize. Architecture, devices, etc. are all factors that affect the final performance of the chip. Also known as a 4nm process chip, the chip process details of TSMC and Samsung are also very different. With the continuous evolution of Moore's Law, the reduction of chip size has been very limited, which can no longer be the only criterion for measuring the evolution of the chip process.