In the future, the urban population has soared to 80 million, and small cities cannot accommodate such a huge population, so managers have creatively proposed a new idea - to make the city a three-layer fold. This is the plot of the science fiction novel "Folding Beijing", and its fantasy imagination is breathtaking.
Whether our cities are heading for folding is unknown, but stacking in the chip field has taken the lead in foreseeing the "future".
With the continuous promotion of 5G, AI, Internet of Things and other technologies, we have more and more types of smart products at our fingertips, and the functions are more powerful, and at the same time, huge amounts of data are poured into the network, which puts forward higher requirements for chip computing power. How to cope with the exponential increase in the demands of complex computing? The heterogeneous packaging technology of 2.5D/3D IC has attracted more and more attention from the industry.
On April 7th, the "Siemens Next Generation 2.5 D/3D IC Heterogeneous Packaging Solutions" webinar will be launched, inviting you to discuss the development trend of advanced packaging with experts, Siemens EDA experts will bring the most profound cutting-edge insights and the latest solutions in the industry to solve the problems encountered in the design, simulation and testing of 2.5D/3D IC heterogeneous packaging chips. Help chip practitioners grasp the opportunity and take the lead in meeting the future.
Heterogeneous packaging is good, but it also faces new challenges
Chip packaging technology has come all the way, and heterogeneous packaging represented by 2.5D/3D IC has become the focus of future development. But the implementation of new technologies faces many thorny issues.
First, after the 2.5D/3D stack, the heat generation becomes more concentrated due to the significant increase in integration. At this time, how to achieve efficient heat dissipation and avoid overheating and failing the chip?
Secondly, in the process of chip, intermediary layer, substrate expansion and cold contraction, how to ensure the reliability of mechanical stress?
In addition, can the high-frequency signals between chips meet the timing and signal integrity requirements?
Finally, after the chip stacking is completed, how to test whether the upper chip can work properly, whether the wiring is good, and whether it is not damaged during the stacking process?
Compared with traditional packaging technology, 2.5D/3D IC heterogeneous packaging is not only an innovation in the technology of the packaging factory, but also a challenge to the original design process, design tools, simulation tools, etc.
Siemens EDA – for breaking the game
In the face of many difficulties, many manufacturers are actively developing some solutions, but sometimes manufacturing alone cannot solve the problem. For example, the left shift often mentioned in chip design is to avoid the chip before making the problem. It is necessary to make a digital twin in advance at the time of design, and to identify and solve the problem in advance through simulation verification to minimize potential risks.
And that's where Siemens EDA comes in. Whether on the design side or on the manufacturing side, Siemens EDA is actively working with the relevant manufacturers to find solutions and provide them with ecosystem support.
New exploration, empowering the "core" future
As an industry leader, Siemens EDA has accumulated years of advanced packaging, has a mature set of end-to-end targeting solutions, providing heterogeneous planning and prototyping in the design process, providing a high-speed 3D electromagnetic field simulation tool platform in the analysis process, supporting high-frequency parasitic parameter extraction in the package, and signal integrity and power integrity simulation; providing the physical implementation of the silicon intermediate layer and package in the implementation link; and providing 2.5/3D DRC and LVS in the verification process, which has been recognized by the industry. Among them, the high-density advanced packaging solution passed Samsung Foundry's latest packaging process certification and obtained the 2020 Samsung Foundry's MDI (Multi-Core Integrated) packaging process certification.
In 2020, Siemens EDA won TSMC's OIP Partner of the Year Award for Jointly Developing 3DIC Design Productivity Solutions for its leading solutions, and will further cooperate with TSMC to realize next-generation SoC and 3DIC designs through solutions that support TSMC's latest technology certification; in 2021, Siemens EDA will once again join hands with TSMC to design IC on the cloud and TSMC's 3D silicon stacking and advanced packaging technology series - 3D Fabric Key milestones have been reached.
In the future, Siemens EDA will continue to explore, comprehensively using electronic and system machinery tools, and providing more solutions for manufacturers from the perspective of chip as a whole. At the same time, by participating in the development of chip-to-chip communication signal connection standards, it promotes the integration of 2.5D/3D IC heterogeneous packages for a wide range of applications.
Want to know more?
On April 7th, webinar on "Siemens Next-Generation 2.5D/3D IC Heterogeneous Packaging Solutions"
Our EDA experts are online to answer your chip package design questions.