01
The basic concept of reflux
In the schematic of a digital circuit, the propagation of a digital signal is from one logic gate to another, and the signal is sent from the output to the receiving end through a wire, which seems to flow in one direction, so many digital engineers believe that the loop path is irrelevant.
After all, both the driver and receiver are specified as voltage mode devices, so why consider current?
In fact, basic circuit theory tells us that signals are propagated by electric currents, specifically, the movement of electrons. One of the characteristics of the flow of electrons is that electrons never stay anywhere, and no matter where the current flows, it must come back. Therefore, the current always flows in the loop, and any signal in the circuit exists in the form of a closed loop.
For high-frequency signal transmission, it is actually the process of charging the dielectric capacitor that is sandwiched between the transmission line and the DC layer.
02
Effects of reflux
Digital circuits typically use ground and power planes to complete the backflow. The return path of high-frequency signals and low-frequency signals is not the same, and the low-frequency signal return selects the path with the lowest impedance, and the high-frequency signal return selects the path with the lowest inductance.
When the current starts from the driver of the signal, flows through the signal line, and injects into the receiving end of the signal, there is always a return current in the opposite direction: starting from the ground pin of the load, passing through the copper plane, flowing to the signal source, and the current flowing through the signal line forms a closed loop.
The noise frequency caused by this current flowing through the copper plane is comparable to the signal frequency, and the higher the signal frequency, the higher the noise frequency.
Instead of responding to an absolute input signal, the logic gate responds to the difference between the input signal and the reference pin. The circuit at the point termination reacts to the difference between the incoming signal and its logically reference plane, so perturbations in the ground reference plane and interference in the signal path are equally important. The logic gate responds to the input pin and the specified reference pin, and it is not clear which is the specified reference pin (for TTL, usually a negative supply; for ECL it is usually a positive supply, but not all of them), and in this way, the immunity of the differential signal has a good effect on ground bounce noise and power plane sliding.
When many digital signals on the PCB board are switched synchronously (such as the CPU's data bus, address bus, etc.), this causes transient load current to flow from the power supply to the circuit or from the circuit to the ground, due to the impedance of the power line and the ground, synchronous switching noise (SSN) will occur, and the ground plane rebound noise (referred to as ground bounce) will also occur on the ground line. When the surrounding area of the power line and ground wire on the printed board is larger, the greater their radiation energy.
Therefore, we analyze the switching state of the digital chip and take measures to control the return mode to achieve the purpose of reducing the surrounding area and minimizing the degree of radiation.
illustrate:
IC1 is the signal output, IC2 is the signal input (to simplify the PCB model, it is assumed that the receiver contains a down-to-wall resistor), and the third layer is the ground layer. The ground of IC1 and IC2 both comes from the third layer of the ground plane. The upper right corner of the TOP layer is a power plane connected to the positive power supply. C1 and C2 are decoupling capacitors for IC1 and IC2, respectively. The power supply and pin of the chip shown in the figure are the power supply and ground of the sending and receiving signal terminals.
At low frequencies, if the S1 terminal outputs a high level, the entire current loop is the power supply through the wire to the VCC power plane, then through the orange path into IC1, then out of the S1 end, through the second layer of the wire through the R1 end into IC2, then into the GND layer, through the red path back to the power supply negative.
At high frequencies, the distribution characteristics of the PCB can have a great impact on the signal. What we often call ground return is a problem that is often encountered in high-frequency signals. When there is an increased current in the signal line from S1 to R1, the external magnetic field changes quickly, which will make the nearby conductor induce a reverse current, if the ground plane of the third layer is the complete ground plane, then it will produce a blue dotted current on the ground plane, if the TOP layer has a complete power plane, there will also be a return flow along the blue dotted line in the TOP layer. At this time, the signal loop has the smallest current loop, the least energy radiated outward, and the ability to couple external signals is also minimal. The skin-catching effect at high frequencies is also the smallest outward radiation energy, and the principle is the same.
Because the high-frequency signal level and current change are very fast, but the change period is short, the energy required is not very large, so the chip is the closest decoupling capacitor to the chip. When C1 is large enough and reacts fast enough (with a very low ESR value), the orange path at the top and the red path at the GND layer can be considered non-existent (there is a current corresponding to the supply of the entire board, but not to the signal shown).
Thus, according to the environment constructed in the figure, the entire path of the current is: the yellow path via capacitance negative of the GND layer of the GND via gnd layer of the GND via of the positive electrode IC1 of C1 ic1 is: the GDC1L2 signal line of C1.
It can be seen that there is a brown equivalent current in the vertical direction of the current, and the magnetic field will be induced in the middle, and this torus can also be easily coupled to external interference.
If the signal in the figure is a clock signal, there is a set of 8bit data lines in parallel, powered by the same power supply on the same chip, and the current return path is the same.
If the data line level is flipped in the same direction at the same time, a large reverse current is induced on the clock, and if the clock line is not well matched, this crosstalk is enough to have a fatal effect on the clock signal. The intensity of this crosstalk is not proportional to the absolute value of the high and low levels of the interference source, but is proportional to the current rate of change of the interference source, and for a purely resistive load, the crosstalk current is proportional to:
dI/dt=dV/(T 10%-90%*R)
In the formula, dI/dt (current change rate), dV (swing of the interference source) and R (interference source load) are all parameters that refer to the interference source. In the case of capacitive loads, dI/dt is inversely proportional to the square of T 10%-90%.
As can be seen from the equation, the low-frequency signal is not necessarily less crosstalk than the high-speed signal. That is what we are saying: the signal at 1KHz is not necessarily a low-speed signal, and the situation along the edge should be considered comprehensively. For signals with steep edges, there are many harmonic components, and there is a large amplitude at each octave point.
Therefore, when selecting a device, we should also pay attention to it, do not blindly choose a chip with fast switching speed, which is not only costly, but also increases crosstalk and EMC problems.
Any adjacent power plane or other plane, as long as there are suitable capacitors at both ends of the signal to provide a low reactance path to GND, then this plane can be used as the return plane of this signal. In ordinary applications, the corresponding chip IO power supply is often consistent, and the respective power supply and ground generally have 0.01-0.1uF decoupling capacitors, and these capacitors are also at both ends of the signal, so the return effect of the power plane is second only to the ground plane. Borrowing other power planes for reflux, there is often no low reactance path to ground at both ends of the signal. In this way, the current induced in the adjacent plane looks for the nearest capacitor back to ground. If this "nearest capacitor" is far from the beginning or terminal, the return also has to go through a "long journey" to form a complete return path, and this channel is also the return path of the adjacent signal, and the effect of this same return path and common ground interference is the same, equivalent to crosstalk between signals.
For some unavoidable cross-power splits, high-pass filters can be formed by spanning capacitors or RC series in series at the cross-segment (such as 10 ohm resistor string 680p capacitors, the specific value depends on their own signal type, that is, to provide a high-frequency return path, but also to isolate low-frequency crosstalk between each other planes). This may involve the problem of adding capacitance between the power planes, which may seem a bit comical, but it certainly works. If some specifications do not allow it, the capacitance can be introduced to ground in two planes at the partition.
For the case of borrowing other planes for reflux, it is best to add a few small capacitors to ground at both ends of the signal to provide a return flow path. However, this approach is often difficult to achieve. Because most of the surface space near the terminal is occupied by the matching resistor and the decoupling capacitance of the chip.
Reflux noise is one of the main sources of noise in the reference plane. Therefore, it is necessary to study the path and flow range of the return current.
03
Theoretical knowledge of the backflow path
In the figure below is a line in the printed board, there is current passing through the wire, usually, we only see the wire applied to the surface for transmitting the signal, from the drive end to the receiving end, in fact, the current is always on the loop to flow, the transmission line is what we can see, and the current return path is usually invisible, they usually flow back with the help of ground plane and power plane, because there is no physical line, the loop path becomes difficult to estimate, and it is difficult to control them.
As shown in Figure 3.1, each wire on the PCB board and its loop constitutes a current loop, according to the principle of electromagnetic radiation, when the mutated current flows through the wire loop in the circuit, it will produce an electromagnetic field in space and affect other wires, which is what we usually call radiation, in order to reduce the impact of radiation, first of all, the basic principles of radiation and parameters related to radiation intensity should be understood.
Figure 3.1 Differential mode radiation on a printed board
These loops act as small antennas at work, radiating a magnetic field into space. We simulate it with the radiation generated by the small loop antenna, setting the current to I, the small ring with an area of S, and the intensity of the electric field measured in the far field of r in free space is:
Equation 3.1 applies to small rings placed in free space and no reflection on the surface, in fact our products are carried out on the ground rather than in free space, and the reflection of the nearby ground will increase the measured radiation by 6dB, taking this into account, Equation 3.1 must be multiplied by 2, if the ground reflection is corrected and assumed to be the maximum radiation direction, then Equation 3.1 is:
As shown in Equation 3.2, the radiation is proportional to the loop current and the ring area and proportional to the square of the current frequency.
The path of the return current in the printed circuit board is closely related to the frequency of the current. According to the basic knowledge of the circuit, DC or low frequency current always flows in the direction of the least impedance, while the high frequency current always flows in the direction of the least inductive impedance in the case of a certain resistance.
If the influence of the hole and groove formed by the vias on the copper laying plane is not taken into account, the path with the least impedance, that is, the path of the low-frequency current, is composed of arc lines on the copper plate, as shown in Figure 3.2. The density of the current on each arc is related to the resistivity on this arc.
Figure 3.2 High-frequency current path on the copper platen of a PCB
For the transmission line, the return path with the smallest sensitivity, that is, the high-frequency current return path, is on the copper plate directly below the signal routing, as shown in Figure 3.3. Such a return path minimizes the space area surrounded by the entire loop, which minimizes the magnetic field intensity (or ability to receive space radiation) radiated by the ring antenna formed by this signal into space.
For longer, straight wiring, it can be regarded as an ideal transmission line. The signal return current propagated on it flows through a ribbon area with the signal routing as the central axis, and the farther away from the signal routing center axis, the smaller the current density.
Figure 3.3. This relationship approximates satisfied Equation 3.3:
Equation 3.3
Figure 3.3 Transmission line returns a current density distribution plot
According to Equation 3.3, Table 3.1 lists the return current flowing through the ribbon area centered on the center of the transmission line and the width as a percentage of all return currents.
Assuming inches, the current returned through an area 0.035 inches away from the transmission line accounts for only 13% of all return currents, and only 6.5% is specifically divided into one side of the transmission line, and the density is very small. Therefore negligible.
brief summary:
When there is a continuous, dense, and complete copper laying plane under the signal routing, the noise interference of the signal return current to the copper laying plane is local. Therefore, as long as the principle of localization of layout and wiring is followed, that is, the distance between the digital signal line, the digital device and the analog signal line, and the analog device is artificially opened to a certain extent, the interference of the digital signal return current on the analog circuit can be greatly reduced.
High-frequency transient return current flows back to the drive end via a plane (ground plane or power plane) immediately adjacent to the signal trace. The end load of the driver signal trace, spanning between the signal trace and the plane (ground plane or power plane) immediately adjacent to the signal trace.
When the surrounding area of the power line and ground wire on the printed board is larger, the greater their radiation energy, so we can control the degree of radiation by controlling the return path to minimize the surrounding area.
04
A solution to the backflow problem
There are usually three aspects to causing reflux problems on the PCB board: chip interconnect, copper cutting, and via jumping. These factors are analyzed below.
4.1 Backflow problems caused by chip interconnects
When the digital circuit is in operation, a transition between high and low voltages occurs, which causes transient load current to flow from the power supply to the circuit or from the circuit to ground.
For digital devices, its pin input resistance can be considered infinite, equivalent to an open circuit (i.e., i=0 in the figure below), in fact, the loop current is returned by the distributed capacitance and distributed inductance generated by the chip with the power supply and ground plane. The following is an example of an internal circuit with a collector output circuit as an output signal.
4.1.1 The drive side changes from low to high
When the output signal jumps from low to high, it is equivalent to the output pin outputting a current to the transmission line, because the input resistance is infinite, we think that for the chip, there is no current flowing from the input tube leg, that is, this current must be returned to the power pipe leg of the output chip.
The signal trace is immediately adjacent to the power plane
The driver terminal charges the signal trace and the transmission line composed of the power plane and the terminal load, and the current enters the device from the power pin of the driver and flows from the driver output to the load end;
The high-frequency transient return current flows back to the output of the driver on the power plane below the signal walk line, and the return current flows directly through the power plane and enters the driver from the power pins of the driver, forming a current loop.
The signal trace is immediately adjacent to the ground plane
The driver charges the signal trace and the transmission line composed of the power plane and the terminal load, and the current enters the device from the power pin of the driver and flows from the driver output to the load end;
The high-frequency transient return current flows back to the output of the driver on the ground plane below the signal walk line, and the return current must be crossed from the ground plane to the power plane from the ground plane to the power plane at the drive output with the help of the coupling capacitor at the drive output, and then enter the driver from the power pins of the driver, forming a current loop.
4.1.2 The drive side changes from high to low
This is equivalent to the output pin absorbing current on the transmission line.
The load discharges the transmission line composed of the signal trace and the power plane and the driver output end, and the current enters the device from the output pin of the driver, flows out of the ground pin of the driver, enters the ground plane, and crosses the power plane and the ground plane coupling capacitor near the driver ground pin to return to the load end; the high-frequency transient return current flows back to the load end on the power plane below the signal walk line, forming a current loop.
The load discharges the signal trace and the transmission line composed of the power plane and the driver output, and the current enters the device from the output pin of the driver, flows out of the ground pin of the driver, enters the ground plane, and returns to the load end; the high-frequency transient return current flows back to the load end on the ground plane below the signal walk line, forming a current loop.
Near the output pin and ground pin of the driver, the coupling capacitors of the power plane and the ground plane should be laid to provide a return path for the return current, otherwise, the return current will find the nearest coupling path of the power plane and the ground plane for return (making the return flow path difficult to predict and control, thus causing crosstalk to other traces).
4.2 Solution to the problem of reflux caused by copper clad cutting
Ground planes and power planes reduce voltage losses caused by resistors. As shown in the figure, the loop current flows back through the ground, due to the presence of resistance R1, it is bound to produce a voltage drop at 1 and 2 points, the larger the resistance, the greater the voltage drop, causing inconsistencies to the ground level, if there is a ground plane, it can be regarded as a signal line with infinite line width and small resistance. Loop current always flows through the formation closest to the signal, and when there is more than one layer in the local layer, if the signal is between two ground planes and the two are exactly the same, the loop current will pass through the two planes equally.
4.2.1 Under the condition of localization of layout and wiring,
The digital ground plane and the analog ground plane are common to the same copper plane, that is, the digital ground and the analog ground are not distinguished, and the noise of the digital circuit itself does not bring additional noise to the analog circuit system.
4.2.2 In digital and analog hybrid circuit systems,
The colocation of digital ground and analog ground is selected outside the board, that is, the two copper planes are completely independent, so that the signal line between the digital circuit and the analog circuit does not have the characteristics of the transmission line, which brings serious signal integrity problems to the system. Digital circuit and analog circuit using the same power supply system, ground plane without division, in the design of digital, analog hybrid circuit system, on the basis of layout modularization, wiring localization, digital circuit module and analog circuit module common a complete, undivided voltage reference plane, not only will not increase the interference of digital circuit to the analog circuit, due to the elimination of the signal line "across the groove" problem, can greatly reduce the signal between the crosstalk and the system ground bounce noise, improve the accuracy of the front-end analog circuit.
4.3 Solution to the reflux problem caused by vias
In the printed board signal wiring, if it is a multi-layer board, many signals must be through the layering to complete the connection task, then a large number of vias are used, the impact of vias on the reflux has two kinds: one is the vias to form grooves to block the return flow, and the other is the return layer flow caused by the vias.
4.3.1 Grooves formed by vias
In the printed board signal wiring, if it is a multi-layer board, many signals must be through the layering to complete the connection task, then a large number of vias are used, if the vias in the power supply or ground plane arrangement is more dense, sometimes there will be many vias connected into a piece, forming a so-called groove, as shown in the figure. First, we should analyze this situation to see if the backflow needs to go through the groove, and if the backflow of the signal does not need to go through the groove, it will not hinder the return flow. If the loop circuit is to bypass this ditch to return, the antenna effect will increase sharply, causing interference to the surrounding signal. Usually, after the coating data is generated, we can adjust the place where the vias are too dense and the grooves are formed, so that there is a certain distance between the vias.
4.3.2 Layer hopping phenomenon formed by vias
Let's take the six-layer board as an example for analysis. The six-layer plate has two coating layers, the second layer is the formation layer, and the fifth layer is the power supply layer, so the signal return of the surface layer and the third layer is mainly in the formation; the return of the bottom layer and the fourth layer is mainly in the power supply layer.
There are six possibilities for changing layer wiring:
Surface layer third layer
Surface layer fourth layer
The bottom layer of the surface layer
The third layer is the fourth layer
The third floor
The fourth floor
These six possible situations can be divided into two categories according to the situation of the loop current: the loop current flows on the same layer and on different layers, that is, whether there is a layer hopping phenomenon.
When loop current flows on the same layer
It includes the third layer of the surface layer and the bottom layer of the fourth layer.
In this case, the loop current is flowing on the same layer, but, from the principle of electrostatic induction, it can be seen that the complete conductor in the electric field has an internal electric field strength of zero, and all the current flows on the surface of the conductor, and the ground plane and the power plane are actually such a conductor.
The vias we use are through holes, and the holes left by these vias when they pass through the power supply and ground plane pass through the path of current on the upper and lower surfaces of the coating layer, so the return flow path of these signal lines is very good and does not need to be improved by taking measures.
The case when the loop current flows on different layers
Including the surface layer of the fourth layer, the surface layer of the bottom layer, the third layer of the fourth layer, the third layer of the bottom layer.
The following takes the bottom layer of the surface layer and the third layer of the fourth layer as examples to analyze their reflux.
Signals with a layer-skipping phenomenon require some bypass capacitance, typically 0.1uf, near the overwell dense region to provide a return flow path.