Author | Fu Bin
Source | Fruit shell hard technology
Since 1997, the traditional nanonumeric-based method of naming process nodes no longer corresponds to the actual gate length of a transistor.
Now, from the CPU to the GPU, you will hear words like 10nm, 7nm, 5nm. This reference number makes it easy to intuitively understand process progress, and consumers generally use this number to select products.
But behind such a simple number, there are some "catty", and some manufacturers have taken advantage of the loopholes behind it to play word games.
Game for the rich
What exactly is the concept of nano? 1nm is equivalent to one-ten-thousandth of a hair thickness, figuratively speaking, a 1nm object is placed on a ping-pong ball, just like a ping-pong ball is placed on the earth.
While the diameter of the silicon atom is 0.117 nm, 5 nm means only about 43 atoms in size, and 3 nm is only about the size of about 26 atoms. Chip practitioners are sculptors who walk in the microscopic world.
The nano-digits used by the manufacturers here are a kind of numbers used to distinguish the chip process, also known as the process.
The process directly affects the performance of the chipset, power efficiency and volume, it is generally 28nm as a watershed, distinguishing between advanced processes and mature processes, the former is mostly used in areas with higher requirements for computing performance, and the latter is used in scenarios with higher costs.
While both processes are important, more advanced processes represent the hard power of manufacturers.
How did this string of numbers come about?
The earliest reference to the process was the physical characteristics of the transistor, including the gate length and the transistor half-pitch, the gate length is used to measure the distance between the source and drain of the two-dimensional transistor transistor, and the transistor half intercept refers to half of the distance between the interconnect lines inside the chip, that is, half of the lithography spacing.
Schematic diagram of different transistor structures, source: Lam Semiconductor
The evolution of the process is actually the result of a self-driven prediction of Moore's Law.
In order to achieve the Definition of Moore's Law for doubling the transistor capacity of the chip every 18 to 24 months, the gate length and transistor half-intercept need to increase by about 0.7 times on each node, and the result of the calculation is arranged as the most primitive process node.
Process nodes divided in Moore's Law, Source: WikiChip Analysis
While there are many benefits to improving the process, it is an expensive game for manufacturers. DIGITIMES estimates that the investment in a 28nm fab is $6 billion, and the investment in a 5nm fab is as high as $16 billion.
According to IBS data, the design cost of 3nm chips reached 500 million to 1.5 billion US dollars, and the cost of building a 3nm production line was 15 billion to 20 billion US dollars.
At present, only TSMC, Samsung and Intel are left on the stage to compete for the top advanced process.
Map of the distribution of players in different processes, source: Wikipedia
Who's playing word games
Back in 2014, Intel (INTC.US) was still the hegemon of the process, taking the lead in entering the 14nm process that year. After a year, Samsung and TSMC launched 14nm and 16nm processes respectively, but what they never expected was that this became Intel's last glory.
In 2017, Samsung and TSMC successively announced that the 10nm process had entered the mass production stage, but at this time Intel could only add a "+" sign after 14nm.
In March 2017, Mark Bohr, then senior researcher and director of process architecture and integration, noted on Intel's website that the industry needed a new degree-based approach to level the playing field and allow customers to easily compare different chip processes.
He proposed that standardized density indicators could be used as a new process measurement method, and also released a planning map of crystal density at different process nodes, showing that other manufacturers had long deviated from the landing point where the process should be.
In other words, other vendors are simply playing word games. At that time, this picture also seemed to be an oath that Intel's 10nm would be available in 2018.
Intel published a transistor density map, image source: Intel
Then, in September 2017, Intel held a press conference to launch its own 10nm process, rarely comparing TSMC and Samsung side by side, and when asked why it pointed directly at friends, Intel said: "Tigers don't threaten, when I am a sick cat?" ”
Intel published a comparison of 10nm technology density, Image source: EDN China
But since then, Intel's 10nm has never been heard again, and 10nm has become a hurdle that Intel can't get over. Finally, looking back, I found that in the 14nm node for many years, only 14nm+ and 14nm++ were made, and the nickname of "toothpaste factory" was dropped.
By 2019, Intel finally mass-produced 10nm, but the world has changed, Samsung and TSMC's process has reached 7nm/6nm, and 5nm is ready to go.
In fact, Intel is conservative about the term nanodials.
According to EETimes China analysis, Samsung is aggressive in the naming of the process, if by Samsung's standards, Intel's 14nm+++ (Intel's early planned process, not officially released) can be named 12nm, or even 10nm.
At HotChips31 (2019), Philip Wong, vice president of research at TSMC, said that how many nanoscales now represent only technical iterations, just like the car model is not clear, so please don't confuse the node with the name of the technology that actually provides it.
A year later, Godfrey Cheng, head of marketing at TSMC, also admitted that from 0.35 μm (350 nm), nanodirections no longer really represent physical scales, but are just an industry standardization term. He agreed with Mark Bohr that process nodes required a whole new descriptive language.
Intel, which did not participate in word games, officially "counterattacked" in July 2021, introducing a new naming system, renaming the original 10nm Enhanced SuperFin to Intel 7, renaming 7nm to Intel 4, and then continuing this naming method as Intel 3, Intel 20, and Intel 18 (that is, Amy, 10 Esm = 1 nanometer).
This time, Intel has also joined the ranks of word games, and even created an Amy-level naming method. In addition, according to Moore's Law calculations, there will indeed be numbers such as 1.8nm, 1.3nm, 0.9nm, and Amy can also avoid the occurrence of decimal points, killing two birds with one stone.
Comparison table of process nodes of the three major manufacturers from 2011 to 2025
Source 丨Guohai Securities Research Institute, Yuanchuan Internet Group, the official websites of various companies
Deviation of the curve
Why are Samsung and TSMC playing word games?
In fact, the gate length and transistor half-intercept are equal at first and correspond to nanodirects.
But since 1997, the traditional nanonumeric-based process node naming method no longer corresponds to the actual gate length of the transistor, and after 14 nm, these numbers have almost no physical significance, only equivalent to a code name.
If the geometric scaling can really be synchronized with the actual feature size, then in 2015, the industry will enter the era of 1nm manufacturing.
Well below 1nm before 2015? Delightful Fantasy, Source: ExtremeTech
In 2011, for example, Intel switched to a FinFET structure on a 22nm node with a gate length of 26nm, a half-pitch of 40nm, and a fin of 8nm.
Process, half-intercept and gate length comparison table, Source: IEEE
Continuing to use nanonumers without physical significance is actually confusing. On the one hand, it will make people think that it is a physical geometric miniature, on the other hand, it will make people misunderstand that semiconductor technology has reached the physical limit.
Intel, Samsung, TSMC transistor density comparison chart, source: WikiChip Analysis
Through comparison, it is found that the transistor density of the same generation of process Intel is nearly double that of TSMC. When Intel renamed its 10nm to Intel 7, the transistor density was still comparable to TSMC's 7nm.
For TSMC, the performance has improved compared to the previous generation, and this number has nothing to do with physics, even if it is not at the correct Moore's Law corresponding point, so there is no problem in calling it.
Industry insiders pointed out that the conversion of Intel's process into an "equivalent node" (EN) is expected to be 4.1 nm of Intel's original planned EN value of 7nm, between 5nm and 3nm of Samsung and TSMC; Intel's original planned EN value of 5nm is 2.4nm, between 3nm and 2nm of Samsung and TSMC.
Tom's Hardware points out that for people who don't know the inside story, Intel's 10nm Superfin architecture sounds far inferior to the TSMC 7nm used by AMD, which is deceptive.
However, it still needs to be pointed out that Intel's 10nm is indeed a little late, and now the transistor density of Samsung and TSMC has long surpassed Intel, lagging behind and squeezing toothpaste is an indisputable fact, and even Intel's current CEO Pat Kissinger also admitted this backwardness, so now Intel will bet its hopes on Intel 20, that is, the original 2nm.
Transistor density comparison of different process nodes in 2021, Source: AnandTech
New rules of the game
Since the use of nanodenteration to measure processes is so misleading, is there any better solution?
In an article by the IEEE, it is recommended to use the LMC density index to measure the basic technology of semiconductors, and the LMC density index is divided into three parts: logic transistor density DL, main memory density DM, and connection density DC between main memory and logic transistor.
Trend chart of logic transistor density, main memory density, and interconnect density, Source: IEEE
While the industry prefers to market its technology with its favorite labels, the LMC density metric, as a common language, provides a more balanced measure of technological progress among semiconductor manufacturers.
Mark Bohr suggested a comprehensive calculation of the density of 2-bit NAND (4 transistors) and SFF (Scan Flip Flop, scanning trigger), and suggested that each chipmaker disclose the density index of "NAND+SFF" in MTr/mm (million transistors per square millimeter) when mentioning process nodes.
At the same time, considering the different processes, it is best to report the size of the SRAM unit separately.
Intel considers a more scientific calculation formula, image source: Intel
While Mark Bohr's previous proposal did make some sense, getting competitors to disclose transistor density and follow their own rules is not something that can be agreed upon in the industry.
On the other hand, Samsung and TSMC, after successfully counterattacking using word games, gradually overtook Intel in density, and it was unrealistic to force opponents to change their names for a while, so Intel had to create a completely different symbol.
From now on, the three major manufacturers will bet on 2nm/Intel 20, and a new round of hegemony is about to start.
Now, from the CPU to the GPU, the words 10nm, 7nm, 5nm are heard, and through this reference number, it is easy to intuitively know the progress of the process, and consumers will generally use this number to select products.