Source: Content by Semiconductor Industry Watch (ID: icbank) original, author: Du Qin, thank you.
Semiconductor engineering has always had three pillars: lithography, transistor design, and materials, and packaging is now the fourth pillar. Most semiconductor devices are encapsulated in ceramic, metal, or plastic to prevent damage to the chip and its fragile connections. Despite this important feature, packaging is one of the most overlooked aspects of semiconductor design. But as Moore's Law has reached its limits, packaging has now become a focus on foundries, OSAT, and chip designers, affecting power, performance, and cost at the macro level, and affecting the basic functions of all chips at the micro level.
A brief history of semiconductor packaging development
Semiconductor packaging technology has evolved rapidly since the invention of the first semiconductor packaging in 1965, and thousands of different semiconductor packaging types have evolved. The role of semiconductor packaging is generally three, one is to prevent damage to the chip and the connection line; the second is to realize the electrical connection between the silicon chip and the PCB; and the third is to dissipate heat. There are two main driving forces driving the continuous evolution of semiconductor packaging, one is to solve the high pin count, and the other is to meet the small size requirements.
Semiconductor packaging history (Source: anysilicon)
Next, let's take a closer look at the history of semiconductor packaging. In 1965, three fairchild engineers: Don Forbes, Rex Rice, and Bryant Rogers— invented a 14-pin ceramic dual in-line package (DIP) with two rows of pins, the first true semiconductor package. The DIP package began mass production in the early 1970s. Intel's 8008 was one of the first microprocessors and an iconic DIP-packaged semiconductor.
Intel's original microprocessor, 8008 series
By the 1980s, chips began to get bigger, integrating more functions and introducing chips with 1 million gates. The input and output (IO) of the data on the chip is the lifeblood of computation. To address the increasing number of IOOs, semiconductor packages are introduced in PGA (Pin Grid Array) and BGA (Ball Grid Array) packages. The image below looks like a ball grid array, which mounts a piece of silicon directly to a PCB or substrate from below, rather than just tapeing the corners of all 4 ends as was the case with previous surface mount techniques. The benefit of BGA packaging is that it takes up less space and has more connectivity.
What a ball grid array (BGA) looks like
By the 1990s, the rise of mobile devices such as laptops and mobile phones had led to the gradual development of semiconductor packaging toward miniaturization, so CSP (chip-scale packaging) was introduced to solve the requirements of high pin count and small size. The CSP package is essentially a small size BGA with a small ball pitch.
Later, into 2010, gradually came to the era of advanced packaging, and more and more packaging types appeared, developing into SiP, POP, WLP, and 2.5D and 3D packages. Now that the rise of applications such as 5G and wearables, as well as the increasing demand for small sizes of electronic devices, the industry predicts that advanced packaging such as SiP is gradually becoming the mainstream of the industry.
In terms of 2.5D and 3D packaging, TSMC, Samsung and Intel are at the forefront. TSMC's CoWoS is representative of 2.5D integration, and SoIC is representative of 3D packaging. In recent years, Samsung has also become a foundry partner of many chip designers, X-Cube is its 3D packaging solution, and recently, Samsung officially released a new generation of 2.5D packaging technology "I-Cube4". Last but not least is Intel's Foveros 3D package, Intel has made it clear that packaging is its future focus, Intel CEO Pat Gelsinger pointed out that chip packaging and cutting-edge production methods will help the chip industry maintain and even exceed the speed of moore's law in the next decade.
Packaging is becoming increasingly important
Packaging belongs to the back end of the semiconductor supply chain, and its key metrics are often price and durability. No packaging company in the past was considered as important as the traditional front-end fabrication (i.e., wafer fabrication and wafer sorting) processes. Because relatively speaking, the time and expenditure required for back-end operations are much less, and the capacity expansion of packaging is relatively fast, and people do not realize that it will appear in the supply chain of the card.
But now, as Moore's Law reaches its limits, there are more and more chip design companies, the types and performance requirements of chips are increasing, packaging is now indispensable at all levels, and with the improvement of complexity and profitability, packaging has become an important part of the concerns of chip designers, IDM, foundries, and OSAT.
TSMC has been laying out in advanced packaging for many years, and the investment in packaging has also given it a taste of sweetness in the early days, with the new packaging technology InFO, TSMC won the Apple processor order. TSMC currently has advanced sealing and testing plants in Zhuke, Nanke, Zhongke and Longtan, mainly providing wafer bumps, advanced testing and 3D packaging, and the fifth Zhunan plant under construction, which is expected to be mass-produced in the second half of 2022. Recently, according to the report of The China Times News Network, TSMC or re-construction of advanced packaging factories, it is currently rumored that it may be located in the Yunjia area, of which Chiayi has the best chance of winning.
Samsung has been chasing TSMC for the past few years, especially in the field of advanced packaging. In November 2021, Samsung and Amco jointly developed a new 2.5D packaging solution, the H-Cube (Hybrid Substrate Cube), which is dedicated to areas such as high-performance computing (HPC), artificial intelligence (AI), data center and networking products that require high-performance and large-area packaging technologies. In December 2021, Samsung approved spending $850 million (1.1 trillion won) on equipment and infrastructure to produce flip-chip ball grid arrays (FC-BGA) in Vietnam.
Intel sees the package as a catalyst for product innovation, and as the physical interface between the processor and the motherboard, the package of the chip plays a crucial role in product-level performance. Intel's "Lakefield" processor combines hybrid CPUs with their Coveros 3D package technology. On December 16, 2021, Intel announced that it will invest 30 billion ringgit (about 45.35 billion yuan) in Malaysia over the next ten years to build new state-of-the-art packaging and manufacturing equipment.
Memory vendor SK Hynix is also increasing the value of memory solutions by enhancing packaging competitiveness in traditional packaging, TSV and FO-WLP. A PL of SK Hynix once said, "Packaging technology is very important for the proper operation of high-performance equipment. For example, sending and receiving large amounts of data at the same time requires the formation of an infinite number of electrical paths connected to the outside, and the encapsulation process plays a role. Packaging technology stacks multiple chips to achieve 4x, 16, or even more capacity than traditional chips, or combines multiple types of chips into a single system. In other words, relying on packaging technology, the added value of the product can be greatly increased. Now, without advances in packaging technology, chip technology alone cannot dominate the market in the future. ”
Domestic attack on advanced packaging
Since the mid-1980s, packaging has become a key link in the continental semiconductor supply chain. Now advanced packaging has become the focus of Technology in China's semiconductor industry. Domestic Changdian Technology, Tongfu Microelectric and Tianshui Huatian have already laid out in advanced packaging, not only traditional packaging factories, but also some chip manufacturers and newly emerging packaging forces are moving towards advanced packaging.
On October 15, 2021, Tongxingda Kunshan, a subsidiary of Shenzhen Tongxingda, signed an agreement with Kunshan Riyueguang to cooperate in the "Chip Advanced Packaging and Testing (Gold Bump) Whole Process Packaging and Testing Project". Advanced packaging technology plays an important role in display driver ICs and CIS chips. Chinese mainland Gold Bump has less packaging and testing capacity, especially the Gold Bump packaging and testing capacity directly facing display driver ICs and CIS chips is even more scarce.
SiP packaging is also a major direction for many domestic companies to exert efforts. According to Yole's forecast, the proportion of advanced packaging will increase to 49.4% of the overall packaging and testing industry in 2025, of which SiP packaging is optimistic about the market, and from 2020 to 2026, the SiP market based on overmolding (FC) and wire bonding (WB) will grow to a cagr of 5% to a scale of $17 billion. Over the same period, the embedded die (ED) SiP market will increase to $189 million with a CAGR of 25%, and the fan-out (FO) SiP market value is expected to grow to $1.6 billion at 6% CAGR20-26.
On December 15, 2021, the third phase of The Advanced Packaging and Testing Industrial Base Project of Huayu Electronic Integrated Circuit was started, according to its official micro introduction, the total investment of the third phase of the project was 1 billion yuan, with a total construction area of 45,000 square meters, and the packaging technology was upgraded to SiP system-level 3D packaging technology and LGA and BGA advanced packaging technology, and it is expected to be put into operation in 2022.
Then there is the Moore elite who is exploring the field of SiP fast sealing, it is understood that the Moore elite Wuxi SiP sealing and testing center, the first phase of the total investment of 500 million yuan, construction area of 15,000 square meters. The plant has an annual planned capacity of more than 100 million units, including: FCBGA engineering batch, SiP design and engineering batch, SiP mass production and testing. It is reported that in 2022, Wuxi SiP Packaging and Testing Center can produce complex SiP products with FC+WB technology, and can also produce FC and WB standard products. By 2023, FC+WB+SMT products will be produced. In 2024, the goal of Wuxi SiP Packaging and Testing Center is to develop AiP technology and carry out SiP design and production of electromagnetic isolation technology.
Huawei is also optimistic about this link of packaging, and its Huawei Hubble has invested in a number of manufacturers in the packaging field. Not only that, on December 28, 2021, Huawei also registered 600 million yuan to establish Huawei Precision Manufacturing Co., Ltd. to encapsulate the link. Some Huawei insiders said, "We do not produce chips, and our main business is the precision manufacturing of some core devices, modules, and components of Huawei's wireless, digital energy and other products, including assembly and packaging and testing." The 'semiconductor discrete devices' mentioned in the business scope are mainly the packaging and testing of discrete devices. ”
Source: Qi cha cha
For example, on January 12, 2022, the Ningxia storage core integrated circuit industry research and development project was officially put into production, and 2 micro-assembly production lines and 1 multi-chip packaging line were also officially put into operation. It is reported that the total investment of the project is 400 million yuan, covering an area of 50 acres, and the current investment is 200 million yuan to implement the first phase of the project. The first phase of the project will build three surface mount (SMT) production lines and one integrated circuit packaging production line, mainly producing wireless hotspot filter modules, RF front-end modules, integrated RF switches and filters, and 4K ultra-short-range LED projectors, which are mainly used in smartphones, tablet computers and in-vehicle storage.
epilogue
There is no doubt that packaging, as an important part of the industrial chain, has become the focus of major manufacturers. The slowdown in Moore's Law is driving fundamental change. We are in the midst of a renaissance in semiconductor design driven by advanced packaging.