At this year's 67th International Electronic Devices Conference (IEDM 2021) in San Francisco, California, Samsung and IBM announced in the "3D at the Device Level" discussion that they have worked together to achieve a major breakthrough in the design technology of next-generation semiconductor chips. It is reported that this breakthrough VTFET technology allows transistors to be stacked vertically. Not only does it help to reduce the size of semiconductor chips, but it also makes them more powerful and efficient.
During the conversation
IBM and Samsung explain how semiconductor chips with a reduced footprint can be made more powerful and efficient by changing the circuit from horizontal to vertical.
In the era of Moore's Law "1.0", CMOS transistors in the industry are built horizontally. After decades of countless process advances, we can now put billions of transistors into a tiny chip.
IBM and Samsung Unveil Semiconductor Breakthrough（via）
However, as processes are getting closer to the limits of atoms, the semiconductor industry is moving in a vertical direction. WCCFTech notes that inspired by the trench-based DRAM vertical access transistor, a team of researchers at IBM and Samsung described how they changed the transistor architecture.
Specifically, they used so-called "vertically delivered nanosheets" (VTFETs) and a 45nm nano-gate process on the body silicon to make a complementary metal-oxide semiconductor (CMOS) component.
Previous 2D semiconductor chips were placed horizontally on the surface of the silicon, while the current flowed horizontally. However, thanks to the 3D vertical design, the new technology will help to break through the performance limitations of Moore's Law to achieve greater energy efficiency.
Compared to current fin field-effect transistors (FinFETs), VTFETs are expected to deliver a doubling of performance and an efficiency increase of up to 85%. (The cryptocurrency mining industry is also expected to benefit from this.)
Having figured out the two key factors of gate length and spacer size (which determines gate/transistor spacing), 3D vertical device design schemes allow chipmakers to continue to evolve in the direction of Moore's Law.
In addition, due to reduced static and parasitic losses (SS=69/68 mV/dec and DIBL=).
To test this concept, the researchers used VTFETs to make functional ring oscillators (test circuits). The results showed that the new technology reduced capacitance by 50% compared to the lateral reference design.
Finally, while there is no news yet on when commercial VTFETs will arrive, a number of tech giants, including Intel, have invested heavily in the research of Ethiopian-grade chips.
If all goes well, Intel is expected to release a new generation of semiconductor chips based on the Intel 20A brand in Q4 2024.