The Natural Science Foundation of China (NSFC) released the 2024 Project Guidelines for the Major Research Plan on the Scientific Basis of Frontier Technology of Integrated Chips

Notice on the release of the 2024 annual project guidelines for the major research plan of the scientific foundation of the frontier technology of integrated chips

National Science and Technology King's Plan [2024] No. 135

The National Natural Science Foundation of China (NSFC) is now issuing the 2024 Project Guidelines for the Major Research Plan on the Scientific Foundations of Frontier Technology of Integrated Chips, and applicants and supporting units are requested to apply according to the requirements and precautions described in the project guidelines.

National Natural Science Foundation of China

April 30, 2024

2024 Annual Project Guidelines for the Major Research Program of the Scientific Foundation of Integrated Chip Frontier Technology

The major research plan of "Scientific Foundation of Frontier Technology of Integrated Chips" is oriented to the major strategic needs of national high-performance integrated circuits, focuses on the major basic problems of integrated chips, and promotes the improvement of the research level of chips in mainland China through tackling key problems in the fields of mathematical foundation, key technologies of information science and process integrated physics theory of integrated chips, and provides basic theory and technical support for the development of new paths for chip performance improvement.

1. Scientific objectives

This major research plan is oriented to the cutting-edge technology of integrated chips, focusing on the new problems brought about by the significant improvement of the integration degree (quantity and type) of core grains, and intends to explore the new principles of integrated chip decomposition, combination and integration through the in-depth intersection and integration of integrated circuit science and engineering, computer science, mathematics, physics, chemistry and materials, etc., and develop a new technology path to improve chip performance by 1-2 orders of magnitude based on independent integrated circuit technology, and cultivate a research team with international influence. Enhance the mainland's independent innovation capability in the field of chips.

2. Core scientific issues

This major research project focuses on the following three core scientific questions to focus on the decomposition, combination and integration of integrated chips after the number and types of cores have been greatly increased:

(1) Mathematical description of core grains and combinatorial optimization theory.

This paper explores the abstract mathematical description method of integrated chips and chips, and constructs the mapping, simulation and optimization theory of integrated chips and chips with complex functions.

(2) Large-scale chip parallel architecture and design automation.

Explore the integrated chip design methodology after the greatly improved core-particle integration, study the multi-core interconnection architecture, circuit, placement and wiring methods, etc., and support the design of 100-chip/10,000-core scale integrated chips.

(3) Multiphysics coupling mechanism and interface theory at the core scale.

The mutual coupling mechanism of electrical-thermal-mechanical multiphysics in integrated chips under three-dimensional structure is clarified, and a fast and accurate simulation calculation method of multi-physics and multi-interface coupling at the core scale is constructed to support the design and manufacturing of 3D integrated chips.

3. Research directions funded in 2024

(1) Cultivation projects.

Based on the above scientific problems and guided by the overall scientific goals, in 2024, it is planned to give priority to funding application projects with strong exploratory, original ideas and new technology paths around the following research directions:

1. Core decomposition combination and reusable design method.

The formal description, decomposition-combination theory and modeling methods of integrated chips and chips are studied, and the reusable design methods of cores such as computing/storage/interconnection/power/sensing/RF are studied.

2. Multi-core parallel processing and interconnection architecture.

Research on the high computing power and scalable architecture for 2.5D/3D integration, the interconnection network and fault tolerance mechanism between cores such as computing/storage/communication, and the multi-core heterogeneous compilation tool chain.

3. 集成芯片多场仿真与EDA。

Research on electrical-thermal-mechanical coupling multiphysics calculation methods and fast simulation tools for core scale, synthesis/placement/routing automation design tools for integrated chips, and testability design for integrated chips.

4. Integrated chip circuit design technology.

Research on high-speed, energy-efficient serial/parallel, RF/wireless, silicon photonic interface circuits for 2.5D/3D integration, power management circuits and systems for high-power integrated chips, etc.

5. Integrated chip 2.5D/3D process technology.

Research on the manufacturing technology of large-size silicon substrates (Interposer), high-density and high-reliability 2.5D/3D integration process and materials, heat dissipation methods of 10,000-watt chips, optoelectronic integrated packaging process, etc.

(2) Key support projects.

Based on the core scientific issues of this major research plan, guided by the overall scientific objectives, it is planned to give priority to funding the application projects with good accumulation of previous research results, strong intersectionality, and great contribution to the overall scientific objectives in 2024:

1. Cache coherence and storage system.

The cache coherence mechanism of heterogeneous multi-chip systems is studied, and the multi-level cache architecture of integrated chips, the scalable storage management mechanism, and the memory access optimization strategy and quality of service (QoS) optimization mechanism based on the network-on-chip are explored. The cache coherence access behavior level model between the cores is constructed, which supports the cache coherence between two heterogeneous cores (CPU, GPU, etc.) ≥, the total number of CPU cores ≥ 256, the steady state of ≥ 7 cache lines, the typical delay < 200 cycles, and the open-source function verification simulator.

2. Core decomposition and combinatorial optimization methods.

For the computing scenarios such as end-edge-cloud, this paper studies the theory of core decomposition and combinatorial optimization, explores the functional representation of cores, establishes the mapping of complex applications to cores, studies the stability and robustness theory of mapping, and forms a complete core library construction method. Compared with customized design, the performance loss is less than 20%, and the functional redundancy between the cores is not more than 20%, forming a decomposition and combination tool and open source.

3. Place-and-route method for multi-mask integrated chips.

With the goal of minimizing the number of mask layers and the number of cross-mask interconnects manufactured on silicon substrates, the automatic placement and routing method of multi-mask integrated chips is studied, and the collaborative optimization method of TSV/interconnect/deep groove capacitor process and design is explored, and the integrated chip placement and routing EDA tool that supports ≥4 times the size of the mask area and the total number of interconnects of 100 cores and grains ≥105 is realized and open-sourced.

4. Design for testability of integrated chips.

Research on the test bus architecture of integrated chips with high testability, plug and play and low overhead, break through the bottleneck caused by the limited observable pins, explore the hierarchical test scheduling and fault diagnosis technologies of integrated chips, and realize the open source of EDA tools for testability design, with a ≥99% coverage of interconnection faults and a ≤5% hardware overhead for the test architecture.

5. Energy-efficient chip-to-die interconnect single-ended parallel interface circuits.

Research on energy-efficient, high-density 2.5D parallel interconnect interface circuit technology. Explore energy-efficient transceiver circuits and clock generation circuits with a wide tuning range; Facing a variety of interconnection standards and different channels, the reconfigurable technology of signal coding and equalization circuit is studied. Research on anti-noise technology at very low emission voltage swings. It achieves a single-wire maximum speed of ≥32Gb/s, the best energy efficiency ≤ 0.5pJ/bit, NRZ/PAM compatible interconnect parallel interface circuits, and open-source simulation models.

6. Multi-field simulation algorithm and solver for core scale.

The electrical-thermal-mechanical coupling model for the core integration process is studied, the numerical method of multi-physics simulation of the key structures, materials and interfaces of integrated chips is explored, the automatic partitioning of the computational mesh is realized, and the multi-field simulation solver across the scale is developed and open-sourced, and the calculation accuracy and the error range of the experimental results are less than 10%.

7. Large-size silicon substrate manufacturing technology, warpage model and stress optimization.

Research on the manufacturing technology of large-size silicon substrates (Interposer), construct wafer-level warpage models and stress optimization methods, explore the stress effect mechanism of high-density and high-aspect ratio through-silicon vias (TSV), deep trench capacitors (DTC) and other manufacturing processes, realize the preparation of silicon substrates ≥ 4 times the size of the mask area, and realize the warpage value of 12-inch wafers after deep trench capacitors and through-silicon vias does not exceed 200μm. Wafer-level warpage analysis and prediction models were established, and stress optimization simulation tools were developed and open-sourced.

8. Three-dimensional integration of high-efficiency heat dissipation materials and structures.

The heat distribution characteristics and efficient heat transport mechanism under the strong coupling state of multiple hot spots are explored, the integration of new heterogeneous heat dissipation materials and the regulation method of interfacial heat transport, and the structural design and enhanced heat exchange method of microchannel heat sink are explored. For the 10,000-watt 3D integrated chip system, the power of the core 3D stacked single module is ≥ 2000W, the number of layers is ≥ 3, and the maximum heat flux density is ≥ 1000W/cm2. Completed multi-scale hot spot prediction and heat distribution simulation tools, efficient thermal management design tools, and open-sourced.

(3) Integration projects.

This year, it is planned to select research directions with significant application value and good research foundation for integrated funding, and the specific research directions are as follows:

1. Heterogeneous computing three-dimensional integrated chips.

This paper studies the cross-level collaborative design method of 3D integrated chips, explores the modular combination and optimization methods of heterogeneous chips, and verifies key technologies such as vertical power supply architecture and circuits, automatic placement and wiring of silicon substrates, and high-density core-wafer bonding. Reusable active silicon substrate (Active Interposer) was developed, and the peak communication bandwidth of the 3D stacking interface was ≥1Tbps. The prototype of the heterogeneous computing three-dimensional integrated chip is realized, including at least 4 kinds of chips such as CPU, storage, storage and computing, with a total number of ≥ 16, a total storage ≥ of 512Mb, and a total computing power of ≥ 100TOPS, and the energy efficiency of heterogeneous computing is higher than that of GPU/NPU chips with the same computing power of less than 10nm in the independent process. Complete the application verification of integrated chips in scenarios such as intelligent robots and edge computing.

Fourth, the basic principles of project selection

(1) Closely focus on core scientific issues, pay attention to needs and application background constraints, and encourage original, basic and interdisciplinary frontier exploration.

(2) Priority will be given to funding research projects that can solve key technical problems in the field of integrated chips and have application prospects, and require the project results to be open source within the framework of the major research plan.

(3) Key support projects should have a good research foundation and early accumulation, directly contribute to and support the overall scientific goals, and encourage research institutions and enterprises to apply jointly.　

5. 2024 Funding Plan

There are about 15 cultivation projects to be funded, the average funding intensity of direct costs is about 800,000 yuan/project, the funding period is 3 years, and the research period in the cultivation project application should be filled in "January 1, 2025-December 31, 2027";

There are about 8 key support projects to be funded, the average funding intensity of direct costs is about 3 million yuan/project, the funding period is 4 years, and the research period in the application for key support projects should be filled in "January 1, 2025-December 31, 2028";

It is planned to fund 1 integrated project, the average funding intensity of direct costs is about 15 million yuan, the funding period is 4 years, and the research period in the integration project application should be filled in "January 1, 2025-December 31, 2028".

6. Application requirements and precautions

(1) Application requirements.

Applicants for this major research project shall meet the following conditions:

1. Experience in undertaking basic research projects;

2. Have senior professional and technical positions (professional titles).

Postdoctoral researchers, those who are studying for a graduate degree, and those who do not have a work unit or whose unit is not a supporting unit are not allowed to apply as applicants.

(2) Provisions on limited applications.

Implement the relevant requirements of the "Application Regulations" in the "Application Regulations" of the "2024 National Natural Science Foundation of China Project Guidelines".

(3) Precautions for application.

The applicant and the supporting unit shall carefully read and implement the relevant requirements in the project guide, the "2024 National Natural Science Foundation of China Project Guide" and the "Notice on the Application and Completion of the 2024 National Natural Science Foundation of China".

1. The application for this major research project is paperless. The application submission period is from May 30, 2024 to June 5, 2024 at 4 p.m.

(1) The applicant shall fill in and submit the electronic application form and attachment materials online in accordance with the instructions for filling in the instructions and writing the outline of the major research projects in the network information system of the Science Foundation.

(2) This major research plan aims to strategically guide and integrate the advantages of multidisciplinary related research around the core scientific issues, and become a project cluster. Applicants should formulate the project name, scientific objectives, research content, technical route and corresponding research funds according to the specific scientific problems to be solved in this major research plan and the research direction to be funded announced in the project guidelines.

(3) In the application form, select "Major Research Plan" as the funding category, select "Cultivation Project", "Key Support Project" or "Integration Project" as the subcategory description, select "Scientific Foundation of Frontier Technology of Integrated Chips" as the annotation description, select T02 as the acceptance code, and select no more than 5 application codes according to the specific research content of the application project.

There shall be no more than 2 cooperative research units for cultivation projects and key support projects, and no more than 4 cooperative research units for integrated projects.

(4) At the beginning of the application, the applicant should clearly state that the application is in line with the funded research direction in the project guidelines (indicate the research direction serial number and corresponding content in the guidelines), as well as the contribution to solving the core scientific problems of the major research plan and achieving the scientific objectives of the major research plan.

If the applicant has undertaken other scientific and technological projects related to this major research project, the difference and connection between the application project and other related projects should be discussed in the "Research Basis and Working Conditions" section of the main body of the application.

2. The supporting unit shall, in accordance with the requirements, complete the commitment of the supporting unit, organize the application, and review the application materials. Confirm the submission of the electronic application form and attachment materials of the unit through the information system before 16:00 on June 5, 2024, and submit the project application list of the unit online before 16:00 on June 6.

3. Other precautions.

(1) In order to achieve the overall scientific objectives and multidisciplinary integration of the major research plan, the project leader of the funded project shall undertake to abide by the relevant regulations on data and data management and sharing, and pay attention to the mutual support relationship with other projects of the major research plan during the implementation of the project.

(2) In order to strengthen the academic exchange of the project and promote the formation of the project group and the interdisciplinary and integration of the project, this major research plan will hold an annual academic exchange meeting for the funded projects once a year, and will organize academic seminars in related fields from time to time. The person in charge of the funded project is obliged to participate in the above-mentioned academic exchange activities organized by the steering expert group and the management working group of this major research plan.

(4) Consultation methods.

The Second Division of Interdisciplinary Science of the National Natural Science Foundation of China　　

Contact number: 010-62327780

Source: National Natural Science Foundation of China