IT House December 12 news, according to foreign media VideoCardz reported, Intel today published an article, announced three new technologies that break through Moore's Law. The goal of these technologies is to enable chip technology to continue to evolve beyond 2025.
At the 2021 IEEE International Conference on Electronic Devices, Intel announced a 10-fold increase in interconnect density in a multi-chip hybrid package, a 30-50% increase in transistor density, new power and memory technologies, and quantum computing chip technology.
Intel elaborated on some of the innovative technologies that have been announced so far, including Hi-K metal gates, FinFET transistors, RibbonFETs, etc. In the roadmap, Intel also showcased a variety of chip processes, including the Intel 20A process, which further reduced the size of the logic gate, called Gate All Around.
▲ Three major technological breakthroughs announced by Intel
The following specifics are:
1. Intel's new 3D stacking, multi-chip packaging technology: Foveros Direct
This technology is applied to the mixed packaging of multiple chips, which can combine chips with different functions and different processes in an adjacent or layered manner. Foveros Direct technology increases the density of connection points between the upper and lower chips by a factor of 10, with each connection point being spaced less than 10 microns apart.
This technology closely combines CPU, GPU, and IO chips, while also being compatible with mixed packages from chips from different vendors.
Officials said that the program has high flexibility, allowing customers to flexibly customize chip combinations according to different needs. In addition, Intel is calling on the industry to develop a unified standard to facilitate the interconnection between different chips.
Intel demonstrated ribbonFETs' new transistor architecture in July 2021 as an alternative to FinFETs. The new packaging method allows NMOS and PMOS to be stacked together and tightly interconnected, thereby increasing the transistor density of the chip spatially. This approach increases transistor density by 30 to 50 percent in the face of inconvenient processes, perpetuating Moore's Law.
In addition, Intel also said that two-dimensional materials can be introduced into the manufacture of chips, which can make the connection distance shorter and solve the physical limitations of traditional silicon chips. This two-dimensional material is a single-layer molybdenum disulfide MoS2, which can be applied to the silicon chip connection layer to reduce the spacing from 15nm to 5nm.
2. More efficient power supply technology and DRAM memory chip technology
For the first time, Intel has fabricated CMOS chips with GaN Gallium nitride switches on 300 mm silicon wafers. This power supply technology supports higher voltages, and the finished power management chip can control the voltage of the CPU more precisely and quickly, helping to reduce losses, in addition, the chip can also reduce the power supply components on the motherboard.
Shown on the right side of the figure above is a low-latency memory technology developed by Intel: FeRAM. This chip introduces iron elements into the manufacture of chips, which can greatly improve the read and write speed of memory chips, and complete the reading and writing in 2 nanoseconds. At the same time, FeRAM technology can increase the density of memory chips.
3. Quantum computing chips based on silicon chips are expected to replace MOSFET transistors in the future
With the further increase in transistor density in the future, traditional silicon chips will go to physical limits. At IEDM 2021, Intel showcased the world's first logic device to implement a magnetoelectric spin orbit (MESO) at room temperature. This represents the possibility of making nanoscale quantum computing transistors possible.
Intel and IMEC are making progress in spintronic materials research and expect to be able to manufacture full-featured devices capable of mass production in the future. In addition, Intel demonstrated the fabrication of 300mm wafer quantum computing circuits compatible with current CMOS chips and established future research directions.