On March 3, the world's leading chip manufacturers Intel, TSMC, and Samsung joined hands with the chip packaging and testing leader Sun Moonlight to launch a new universal chip interconnection standard with AMD, Arm, Qualcomm, Google, Microsoft, Meta and other technology industry giants: Universal Small Chip Quick Connect (UCle).
The protocol is designed for chiplets to develop a new open standard for chip interconnects, simplifying processes and improving interoperability between chiplets from different manufacturers. Under this standard, chipmakers can mix and build chips where appropriate.
What is a chiplet? SoC's Gravedigger, Moore's Law's "Continuing Life Dan"
In recent years, as the cost of exploring advanced processes has increased, Moore's Law has become increasingly ineffective. The leading manufacturers in the chip manufacturing industry have been struggling to continue Moore's Law. And the small chip is one of the roads.
The reason why Moore's Law is gradually failing is that photomasks limit the maximum size of a single chip, and chipmakers and designers have to use multiple chips to implement functionality. In some cases, even multiple chips provide the same functionality. This requires that the chip must be miniaturized.
Previously, manufacturers have been using SoC (System-on-Chip) technology to combine different modules. The advantage of this technology is that while increasing the communication speed between modules, it can also achieve low power consumption and low cost. However, in recent years, the difficulty and cost of breaking through advanced processes have been rising.
On the one hand, technological breakthroughs have become particularly difficult, and Intel, which has been working in the field of chip manufacturing for many years, has also encountered bottlenecks in 7nm process technology. Samsung, which currently masters the 5nm manufacturing technology, has also been exposed to product yield fraud. At the same time, the cost of exploring advanced processes is also rising. According to IBS CEO Handel Jones, the cost of designing a 3nm chip was $590 million, compared to just $40 million on average to design a 28nm chip.
Small chips, as the name suggests, are packaged together with multiple chiplets and are interconnected with die-to-die (die-to-die) internal interconnect technology to form a heterogeneous chip. Since the chiplets are smaller, the utilization rate of each wafer is increased, thereby reducing costs. And, thanks to the package of multiple chiplets, they can be flexibly assembled as needed, thereby reducing power consumption.
"Big cake" gradually landed, small chips "barbaric growth"
Nowadays, small chip technology has begun to move from theory to practice, and is truly applied to the design and manufacture of chips under the leadership of some head manufacturers. The pie called "making chips by building blocks" drawn by the original small chip technology is now getting closer and closer to realization.
AMD deployed the Zen2 core based on chip-on-chip technology in the Ryzen3000 series released in 2019; Intel released the Ponte Vecchio with 47 small chips. We can see that whether it is splitting a single-chip CPU or integrating a large number of small chips into packages, small chip technology has gone out of the laboratory and applied to actual production.
But small chip technology to mature, there are still many challenges to face.
In chip-on-chip technology, each die interconnect must take into account the interconnect port and protocol. In the design, it is necessary to take into account many complex factors such as process process, packaging technology, system integration, and expansion. At the same time, it is also necessary to meet the requirements of different fields for information transmission speed and power consumption. This makes the design process of the chip very complicated, and the biggest difficulty in the face of the chip is that there is no unified protocol.
Marvell introduced the MoChi architecture as a small chip model in 2015. Since then, Marvell has been caught in the difficulty of choosing an interface. According to Yaniv Kopelman, Marvell's network CTO, they don't want to use interpolators or InFO-type encapsulation because they don't want to stack up package costs or be tied to a single vendor. In addition, when using small chips, it is necessary to divide the IP in the middle, but where to divide and how to develop the architecture also poses a challenge to the implementation of the final product.
Yaniv Kopelman concludes: "It's easy to build IP in a demo, but there's still a long way to go from demo to production. ”
Over the past five years, chiplets have been a shining star in the chip design industry. More and more manufacturers are starting to use small chips, which makes it more and more common. Manufacturers hope that small chips will solve the problems of manufacturing costs, scalability and other aspects of chip manufacturing.
However, due to the lack of unified standards, the previous agreement of the small chip is like a chaotic "Spring and Autumn Warring States". In this case, chipmakers can't realize their ultimate idea: connecting different architectures, different manufacturers of dies, and customizing them for different scenarios.
The "Spring and Autumn Warring States" ended, and UCle 1.0 was just the beginning
Chip-cap technology has been calling for a unified standard.
Intel has Advanced Interface Bus Technology (AIB), a chip-to-chip PHY level standard with a modular design and IP module library. Moreover, Intel provides free AIB interface licenses to promote the small chip ecosystem.
At the same time, parallel interface standards that can be used on small chips include TSMC's LIPINCON and OCP's BoW.
The parallel interface standards in the physical layer alone are already so diverse, which brings a lot of trouble to manufacturers, making it difficult to promote the small chip ecology.
The chip industry is collectively calling for a unified standard that can enable small chips to end the "Spring and Autumn Warring States" era and achieve "the same track of the car, the same text".
Intel seems to have always been the company that has the best chance of clearing the barriers to the development of small chips. Since taking office in 2021, Intel's new president, Pat, has been emphasizing that Intel should take the path of IDM2.0 and continue to deepen its cultivation in chip manufacturing while having higher openness, which coincides with the concept of small chip technology.
At the Intel Investor Conference on Feb. 18, Intel announced the possibility of mixing x86 architectures with other types of cores for customers who choose to source their IFS services, which may involve chipping technology in the process. At the same time, Intel also disclosed at the conference that it is committed to creating an open ecosystem that is "open, optional, and trustworthy". This blueprint seems to be the foreshadowing of the UCle 1.0 standard that Intel has led today. In fact, the initial version of the UCle1.0 standard came from Intel, which borrowed somewhat from the AIB standard proposed by Intel.
Today, the UCle 1.0 standard that the giants are working together to bring is not technological innovation, but the standardization of technology. This makes manufacturers finally have a common rule when using small chips.
The UCle specification includes both a physical layer and a protocol layer. The physical layer specifies the standards for electrical signals that communicate with each other on the chiplets, the number of physical channels, and the supporting bump spacing. At the protocol layer, the specification defines a higher-level protocol that overrides these signals. This specification will enable all small chips that adhere to it in design and manufacturing to be interconnected.
UCle1.0 designs two levels of standards, "standard package" and "advanced package" according to the complexity.
The "Standard Package" is designed for low-bandwidth devices using traditional organic substrates that will use 16 data channels, follow a bump spacing of 100μm+, and extended channel lengths. This is actually about linking two devices in a contemporary PCle link at very close distances.
Technologies such as EMIB and InFO are covered in the "Advanced Package". Bump spacing between 25μm and 55μm is required, and due to higher density and shorter communication range, the number of data channels will be four times that of a standard package. If this standard is used, the amount of data that can pass through the edge of a 1mm chip per second can reach 1.3TB.
Not only that, but UCle can actually find its own stage outside of the chip. In fact, while UCle's focus is to provide a uniform standard for on-chip interconnects for small chips, that standard includes provisions for external interconnects.
The specification allows the use of retimers to complete transmissions over longer distances at the protocol level, as long as the chip manufacturer wishes. While this allows latency and power to increase over distance, UCle promoters envision server users may need such chip interconnects over long distances.
While the advent of the UCle 1.0 specification has finally solved the problem of spec confusion that has plagued the small chip field for a long time, it is still just the beginning. Some have referred to this standard as the "starting point standard" because it specifies the physical and protocol layers in chip design, which are just two of the four aspects of chip design. Industry leaders are still looking for unity in terms of small chip shape elements to truly build a mix-and-match small chip ecosystem.
On the other hand, the UCle1.0 standard basically only defines 2D and 2.5D chip packages, while more advanced 3D package related standards need to wait to be updated.
Members of the UCle Alliance will be developing the next generation of UCle technology, and the new protocol will be more refined. Although the UCle Alliance has brought together several major leaders in the field of chip design and manufacturing, it can be called a gathering of stars. But if we want this standard to go further, so that the concept of chip manufacturers building a perfect small chip ecology is realized, more people need to participate in the construction of this alliance. Leifeng Network