Intel New Transistor Design Patents:
According to the recently exposed patent documents, Intel is working on the Forksheet transistor, which may be applied to the 2nm process node in the future. The new design places n- and p-type nanosheets close together, with a "wall of insulation" in between, allowing for higher transistor density.
Intel's patent should be based on the partner IMEC's Forksheet. IMEC announced the development of forksheet transistors in 2019, according to IMEC research data, this technology can significantly increase transistor density, and bring 10% performance improvement or 24% energy efficiency improvement, the CPU cache SRAM space can be reduced by 30%.
It's hard to say when the Forksheet transistor will be practical, and research and manufacturing planning for semiconductor technology is a multi-year process. The Intel 7 process (10nm) now used in the 12th Generation Core was first proposed in 2008, and the current Intel CEO, Pat Kissinger, was chief technology officer at the time.
Solidigm Flash Technology Development Direction:
SK hynix founded Solidigm following the acquisition of Intel's NAND Flash and SSD business units. Solidigm now has more than 2,000 employees in 20 locations around the world, as well as a Fab 68 fab (formerly Intel asset) in Dalian, China.
SK hynix and the vast majority of other flash memory OEMs use the Charge Trap charge capture structure, while Solidigm inherits Intel's Float Gate floating gate structure. Solidigm executives said in an interview with Blocks & Files that the charge capture structure can meet the needs of high-end workstations and enthusiast-related fields, while the floating gate structure is scalable and provides higher storage density capabilities, making it more suitable for data center applications. Solidigm doesn't bet all its chips on charge-trapping structures or floating-gate structures.
Intel predicted in 2020 that the total TCO cost of ownership for SSD HDDs would reach a crosspoint in 2022. Solidigm still seems to be struggling to achieve this goal, and the means of this naturally include PLC (5bit/cell) flash memory.
The PLC flash memory, which is still under development, seems to be one reason why Solidigm insists on retaining the floating gate structure: the floating gate structure has a better voltage threshold window and provides sufficient stability. Each cell of PLC flash memory can store 5 bits of data, which is 25% higher than current QLCs. Of course, PLC will also bring performance and durability attenuation, which is not what the average consumer wants to see, but there will be companies interested in it in specific enterprise applications.
Solidigm plans to launch enterprise PCIe 4.0 SSDs in the first half of this year, but consumer PCIe 4.0 SSDs will need to wait until the bill of material costs are the same or very close to PCIe 3.0. Overall, Solidigm's strategy at this stage is similar to the Intel era, still an enterprise priority, cost and capacity priority.