The next technological breakthrough in the chip process is coming.
"Vertical transistor technology breakthroughs can help the semiconductor industry continue its path forward and achieve major improvements, including new chip architectures, handsets with up to a week of standby time, IoT devices with lower energy consumption, and more." On Tuesday, IBM and Samsung proposed a new chip manufacturing process, VTFET, that can be twice as powerful or 85% less energy than FinFETs.
In an effort to fit more transistors into a limited space, the VTFET process solves many performance hurdles that were previously unsolvable. It also allows transistors to use more current while reducing energy waste.
VTFETs have found a way to continue Moore's Law, and we don't know when this process will be able to land and make chips into our hands.
Back in 1965, computer scientist Gordon Gordon Moore first hypothesized that the number of transistors that can fit on an integrated circuit doubles every 18 months, while doubling the speed and storage capacity of computers. This is moore's law famous in the field of semiconductors. At present, the number of transistors that can be crammed into a single chip is almost at its limit.
Image source: wikipedia
But at the same time, the path forward for computing systems has not slowed down. Dynamic AI systems are ready to power every aspect of people's lives, from road safety to drug discovery and advanced manufacturing, which will require more powerful chips in the future. So, to continue Moore's hypothetical advances in speed and computing power, we need to make chips with up to 100 billion transistors.
IBM Research, in partnership with Samsung, has made breakthroughs in semiconductor design, claiming to help Moore's Law stay alive for years to come and reshape the semiconductor industry. They propose a new method of stacking transistors vertically on a chip called Vertical-Transport Nanosheet Field Effect Transistor (VTFET). The following is a schematic diagram of a VTFET wafer:
In a new dimension: redefining the boundaries of Moore's Law
Today, mainstream chip architectures use transverse transmission field-effect transistors (FETs), such as fin-type field-effect transistors (FinFETs), so named because the silicon body resembles a fish dorsal fin. FinFETs are designed to layer transistors along the wafer surface, with current flowing horizontally. Unlike this type of design, VTFETs layer transistors in a direction perpendicular to the silicon wafer and allow current to flow up and down in stacked transistors.
The figure below shows a side-by-side comparison of the combined structures of VTFET (left) and transverse FinFET (right) transistors when current is turned on.
This new design approach addresses scaling barriers by relaxing the physical limitations of transistor door length, spacing thickness, and contact size, and optimizes these features in terms of performance and energy consumption.
Below (left) is VTFET designer and project manager Brent Anderson, and (right) is hardware technologist and key R&D member Hemanth Jagannathan, who demonstrates VTFET wafers.
Image source: Connie Zhou
Through VTFETs, IBM and Samsung have successfully demonstrated that it is possible to explore scaling performance beyond nanoslitter technology in CMOS semiconductor designs. On these advanced nodes, VTFETs offer a twice the performance boost or up to 85% reduction in energy consumption compared to the scaled FinFET alternative.
In May, IBM released the world's first chip using a 2nm process process, which can hold 333 million transistors per square millimeter, claiming to be able to integrate 50 billion transistors into a fingernail-sized chip. According to the introduction at the time, ibm's transistors for this 2nm chip adopted a three-stack GAA design.
This time, VTFETs continue technological innovation, opening up new possibilities with the method of vertical stacking transistors.
Explore more space
In the past, designers packaged more transistors onto chips by reducing the gate spacing and routing spacing. This physical space, which fits all components, is called contacted gate pitch (CGP). The ability to reduce the gate and routing spacing has allowed integrated circuit designers to increase the number of transistors that can fit in a device from thousands to millions or even billions.
However, even with state-of-the-art FinFET technology, space for spacing, gates, and contacts is limited. Once the limits of CGP are reached, there is no room for expansion.
FeT configurations that arrange layers horizontally on the wafer. The blue virtual isolation gate in the figure is required to isolate the wasted space to separate adjacent circuits.
VFETs are configured to arrange layers vertically on the wafer, significantly increasing density by reducing the barrier spacing and eliminating the virtual isolation barrier.
Since vertically directional currents, gates, spaces, and contacts are no longer limited by traditional methods, we have more room to expand the CGP while maintaining the position of healthy transistors, contacts, and isolation (isolation and shallow trench isolation, STI). By moving away from lateral layout and current direction limitations, we were able to use larger source/drain contacts to increase the current on the device.
We can also select gate lengths to optimize device guide current and leakage, while isolation layer thicknesses can be independently optimized to reduce capacitance. We don't have to be forced to trade off between gate, isolation, and contact size, which increases transistor speed and reduces power consumption.
Another key feature of VTFETs is the ability to use STI for adjacent circuit isolation to achieve zero diffusion interrupt (ZDB) isolation without losing active gate spacing. In contrast, the density of FET circuits transmitted laterally is affected by the single-double diffusion required for circuit isolation, which affects the ability to further reduce the size of the transistor.
The direction of future chip design
In the Albany lab.
Even a decade ago, we could have felt that horizontal architectures reached scale limits at aggressive gate spacing, and virtually all components in the chip were approaching their limits. IBM's proposed approach is aimed at finding ways to break down these barriers.
Because the gate spacing is more aggressive than any product known in production, and the silicon wafer gate spacing is lower than the 45 nm CMOS logic transistor. IBM believes that VTFET design represents a huge leap forward in building the next generation of transistors, which will enable smaller, more powerful and more energy-efficient devices to emerge in the coming years.
Source: Heart of the Machine