AMD has officially disclosed the planning of the Zen4 architecture, including consumer-grade Ryzen and data center-level Xiaolong, all of which are 5nm processes.
Zen4 products in the desktop named Ryzen™ 7000 series (Raphael), the new AM5 LGA1718 package interface, support dual channel DDR5, PCIe 5.0, released in the second half of the year.
In the data center is the Xiaolong 7004 series (Genoa), the new SP5 LGA6096 encapsulated interface, up to 96 cores and 192 threads, support for 12 channels DDR5, 128 PCIe 5.0, the second half of the year debuted.
There is also a derivative version of Zen4c (Bergamo), optimized for cloud services, with a maximum of 128 cores and 256 threads, launched early next year.
A few days ago, we saw a spy photo of Zen4 Xiaolong, but only the front. Now the new spy photos are coming, and there are all of them.
This is also the first time to see the new SP4 LGA6096 package interface, dense 6096 contacts, divided into four groups, each group is 1524, which is already more than the number of pins (1331) of the AM3 interface.
In fact, the pin/contact definition and mounting bracket structure of the SP5 interface were leaked as early as last year as a manufacturer was hacked.
This sample is an introductory 16-core 32-thread, with a maximum acceleration frequency of 3.7GHz and a thermal design power consumption of 195W, but it is only a sample specification and does not represent the final SKU.
What's more interesting is that at the same time, there are also photos under X-rays, and you can see three chips inside: the largest in the center is the IOD responsible for input and output, and there is a CCD on each side, and obviously each has only 8 cores.
If you want to make up 96 cores, you need 12 CCDs, which is exactly the same as AMD's previously announced schematic layout.
Internal schematic diagram previously published by AMD
Guess the layout of each Zen4 96 core Dragon