Recently, Intel announced the Xeon processor roadmap, the first quarter of this year to deliver Sapphire Rapids, the process, architecture are the same as the 12th generation Core (of course, only large cores), support eight-channel DDR4, PCIe 5.0, optional integration of up to 64GB HBM2e memory. AT THE ISSCC 2022 INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE, Intel generously released the core photos and structure diagrams of Sapphire Rapids, and locuza, the chip god, analyzed it accordingly and labeled each module.
First of all, this time finally clarified the core number of Sapphire Rapids, the actual opening is indeed 56, but the original is not 64, but 60. Sapphire Rapids is packaged in a chip-on-chip package with four dies integrated internally, interconnected via an EMIB bridge.
The same is a small chip, Intel, AMD is taking different routes. AMD separately made the I/O part into a Die chip, Intel is that each Die chip is complete, including all the necessary modules, and even a processor can be taken out separately, so that it is simpler to divide different models.
Each CPU core has 1.875MB L3 cache, the total processor is 112.5MB, and the actual boot is 105MB. PCIe 5.0 and the new CXL 1.1 standard high-speed bus through, basically equal to each other, a total of 128, in addition, UPI interconnect bus a total of 96, but do not know whether all turned on. Memory channels, 128-bit per Die, 160-bit if added ECC error correction.
In addition, Sapphire Rapids integrates a variety of accelerators, including DSA (Data Flow Accelerator), QAT (Fast Assistant Technology), and DLBoost 2.0.
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