A few days ago, Intel announced the Xeon processor roadmap, the first quarter of this year to deliver Sapphire Rapids, the process, architecture are the same as the 12th generation Core (of course, only large cores), support eight-channel DDR4, PCIe 5.0, optional integration of up to 64GB HBM2e memory.
AT THE ISSCC 2022 INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE, Intel generously released the core photos and structure diagrams of Sapphire Rapids, and locuza, the chip god, analyzed it accordingly and labeled each module.
Original kernel photo
Kernel callout diagram
The interconnection of each core to the EMIB bridge channel
First of all, this time finally clarified the core number of Sapphire Rapids, the actual opening is indeed 56, but the original is not 64, but 60.
Sapphire Rapids is packaged in a chip-on-chip package with four dies integrated internally, interconnected via an EMIB bridge.
On the previous dismantling and polishing diagram, it is like each Die 16 cores, four rows and four columns layout, but according to the official kernel photos, one of the pieces is not a CPU core, but a memory controller unit, and the memory PHY physical layer next to it is connected, in fact, each Die is 15 cores (14 open).
It's so confusing
The same is a small chip, Intel, AMD is taking different routes. AMD separately made the I/O part into a Die chip, Intel is that each Die chip is complete, including all the necessary modules, and even a processor can be taken out separately, so that it is simpler to divide different models.
Each CPU core has 1.875MB L3 cache, the total processor is 112.5MB, and the actual boot is 105MB.
PCIe 5.0 and the new CXL 1.1 standard high-speed bus through, basically equal to each other, a total of 128, in addition, UPI interconnect bus a total of 96, but do not know whether all turned on.
Memory channels, 128-bit per Die, 160-bit if added ECC error correction.
Sapphire Rapids also integrates a variety of accelerators, including DSA (Data Flow Accelerator), QAT (Fast Assist Technology), and DLBoost 2.0.
Schematic diagram of the original structure