The AMD Ryzen™ 7000 supports the DDR5-5200 by default:
Arsene has just confirmed that the AMD ZEN4 architecture Ryzen™ 7000 processor will support higher DDR5-5200 memory than Intel's 12th Generation Core by default.
In addition to higher default memory frequency support, AMD is also expected to introduce an automatic memory overclocking technology called EXPO, which allows memory profiles to provide both high bandwidth and low latency presets.
AMD is expected to announce the Ryzen™ 7000 processor at COMPTEX 2022, which will be held at the end of next month, and the product may be launched later.
3D NAND technology innovation: from GAA to trench architecture
The Belgium-based Center for The Study of Microelectronics (IMEC) recently wrote an article on the development trend of 3D NAND flash memory technology and proposed a number of technological innovation research directions. NAND flash memory has entered the 3D stacking era for nearly 10 years, the number of stacked layers has grown from the initial 24 layers to the current 176 layers, and will continue to increase to 500 layers or even 1000 layers in the future, but IMEC has keenly found that by increasing the number of stacked layers alone, it faces the technical challenges of deposition and etching processes, and the 1000 layer stack height may need to be achieved by 2030, resulting in a slowdown in the increase in flash density.
IMEC's research goal is to continue to reduce the xyz length, width and height spacing of flash memory cells under 3D NAND, including replacing the current GAA architecture with a groove architecture. In the new architecture, the flash cells are no longer circular, with two transistors at either end of the groove, which can reduce the xy spacing from the current 140 nanometers to 30 nanometers, enabling higher storage densities.
The Twin BiCS announced by Armored Man in 2019 seems similar. Kaoya claims that the technology can not only increase storage capacity, but also increase write speeds and reduce the level of electronic leakage, but it is not sure when it will be practical.
The groove architecture reduces the xy spacing of the flash memory unit, while the z-spacing reduction requires starting with a new material, replacing tungsten (W) with ruthenium (Ru) and molybdenum (Mo), thereby reducing the vertical word-wire spacing from the current 50 to 60 nanometers to 40 nanometers without increasing resistivity, thereby achieving higher storage density.
In addition to 3D NAND, IMEC is also optimistic about the future development of 3D ferroelectric field effect transistors (3D-FeFETs). 3D FeFETs have better read and write speeds than 3D NAND and have a longer lifespan, making them ideal for low-latency storage.