The imec-ASML and High NA laboratories, which are composed of imec and ASML, have reportedly made progress in developing patterning and etching processes, screening new photoresists and underlying materials, and improving metrology and photomask techniques.
"Imec is working with ASML on High-NA technology because ASML is building its first prototype, the 0.55NA EUV lithography scanner EXE:5000," Imec CEO Luc Van den Hove said, "compared to the current 0.33NA EUV lithography, High-NA EUV lithography expects to print logic chips above 2nm with fewer patterning steps." Our role is to work closely with the global patterning ecosystem to ensure the timely delivery of advanced corrosion-resistant materials, photomasks, metrology techniques, (deformation) imaging strategies, and patterning techniques – fully benefiting from the resolution gain provided by High-NA lithography machines. ”
At this year's SPIE Advanced Lithography Conference, the joint lab will make 12 contributions in the field of High-NA EUV lithography.
Process and material optimization to reduce pattern roughness and defects
In anticipation of the first High-NA EUV prototype system, Imec is improving the resolution capabilities of the current 0.33NA EUV patterning technology to predict the performance of thinner resists for printing fine lines/spaces and contact holes. In addition to pattern collapse, imec identified line edge roughness (LER) as one of the most critical parameters for patterning lines/spaces with a thin resist film and proposed strategies to mitigate pattern roughness (e.g., by adjusting lighting and mask conditions).
In addition, imec and its material suppliers demonstrated results for screening new photoresist materials (e.g., metal oxide photoresists) and substrates with good pattern transfer capabilities under High NA conditions.
They also proposed specialized patterning and etching schemes designed to reduce defects and random printing failures. (Paper No. 12051-7;12055-4;12056-28)
Custom metering to handle small feature sizes with thin resist films and high throughput
In the shift to smaller feature sizes (e.g., 10nm wide lines) and thinner resist films (20nm and below), the industry has faced two important aspects that challenge metrology. First, metrologists need to deal with the significantly reduced image contrast of cd-SEM tools; second, they need to image features smaller than 10nm (given overlay performance, LER, and random print failures) and need metrology tools with higher resolution.
Kurt Ronse, Director of Advanced Patterning Program at Imec, said: "Imec and its partners have taken several directions to address these challenges. They showed that by adjusting the operating conditions of existing metering tools, image contrast could be significantly improved. Supported by deep learning frameworks such as deep learning-based denoising, specialized software further enhances image analysis and defect classification. Finally, in close collaboration with metering suppliers, imec explored alternative metrology techniques for reliably measuring small features, such as high-throughput scanning probe metering and low-pressure aberration correction SEM. (Paper No. 12053-2;12053-3;12053-5;12053-22;12053-43;12053-64)
Solve the specific challenges of high numerical aperture EUV masks
Imec simulated the effect of EUV mask defects (more specifically, mask multilayer ripple and absorption line edge roughness) on 22nm pitch line/spatial imaging.
"It is clear from this study that mask defects are increasingly influencing the final wafer pattern, suggesting that mask design rules need to become more stringent," Adds Kurt Ronse. "These findings allow us to determine the mask specifications for high NA EUV lithography." In addition, together with ASML and our material suppliers, we explored new materials and architectures for mask absorbers that carry this pattern. In this case, we conducted the first exposure to assess the effects of using a low n-attenuation phase shift mask on through-hole layer and line/space imaging. Masks with low n-absorption materials as an alternative to ta-based blanks currently in use have been shown to improve the mask 3D effect on the wafer, helping to increase the depth of high NA focus. (Paper No. 12051-37; 12051-51; 12051-56).
Get ready for the next generation of EUV lithography machines
The semiconductor industry is moving at full speed to develop high-value aperture (high-NA) EUV, but developing next-generation lithography systems and associated infrastructure remains a daunting and expensive task.
For some time now, ASML has been developing its high-value aperture (high-NA) EUV lithography machine, the successor to today's EUV lithography system based on a 0.33 numerical aperture lens. ASML's new high numerical aperture EUV system involves a completely new tool, a lens with a numerical aperture of 0.55 with a resolution of 8 nanometers, compared to the resolution of 13 nanometers for existing tools. Analysts say the 0.55 NA EUV tool is targeting 3nm by 2023, but we don't think the device is likely to be in production before 2025.
According to KeyBanc, the cost of a High NA lithography machine is estimated at $318.6 million, compared to $153.4 million for today's EUV systems. But in fact, the total cost of a lithography system can be higher because we need other new equipment, new photomasks, and different photoresists to achieve high numerical aperture UV. Various vendors are looking at these technologies, but there are still some gaps at this point.
Lithography devices are used to pattern tiny features on a chip, enabling chipmakers to develop smaller, faster devices at advanced nodes and package more features into a single chip or package. Until 2018, chipmakers used traditional optical lithography scanners to pattern features on leading-edge chips. But at advanced nodes, the patterning process of lithography becomes too complex, which creates the need for UV, but this is not enough.
ASML's 0.33 NA EUV lithography machines using 13.5 nm wavelengths are being used by Samsung and TSMC to produce 7nm and 5nm chips. Intel has also added ASML EUV devices to advanced chip production. Samsung and SK Hynix are using UV for DRAM production.
Chipmakers will be using today's UV for a long time. But at some point— such as at a node outside of the 3nm node— it will become more difficult to pattern future chips using existing EIVs. This is where high NA equipment fits.
First, Intel considered the technology critical and announced plans to install ASML's first 0.55 High NA EUV lithography machine.
Ann Kelleher, Senior Vice President and General Manager of Technology Development at Intel, said: "This will lead to a lot of learning, but it will also allow us to continue to evolve to the smallest geometry. ”
Samsung and TSMC will also purchase high-value aperture tools. But the transition to High NA UV involves a variety of new and moving parts. “High
NA reuses a lot of knowledge from 0.33 NA EUV," said Krish Sankar, an analyst at Cowen. "The introduction of EIVs is more challenging for photoresists. The migration to High NA is also more evolved, and the performance of photoresists will continue to improve to meet the imaging requirements of future nodes. Optics with high numerical apertures are new, but they are still reflective optics. ”
Why High NA?
In fabs, chipmakers use lithography and other equipment to produce chips. Using the file format generated during the design phase, the photomask device creates a mask. The mask is the master template for a given chip design that is eventually shipped to the fab. From there, the wafers are inserted into the coater/developer system. The system pours a photosensitive material called photoresist onto silicon wafers.
Then, insert the mask and silicon wafer into the lithography scanner. During operation, the scanner produces light, which is transmitted through a set of projection optics and masks in the system. Light hits the photoresist, forming a pattern on the silicon wafer.
Figure 1: Example of a typical sequence of lithography steps. Source: Chris Mack, Fractilia
For years, chipmakers have used lithography tools based on 193nm wavelengths to pattern advanced chip functions. Through a variety of technologies, chipmakers are extending 193-nanometer lithography to 7nm. But at 5nm, using these techniques is too complicated.
"Printing 50nm, 40nm or 30nm features is an inherently daunting task for 193nm lithography," said Aki Fujimura, CEO of D2S. "Using UV at 13.5 nanometers should be easier and more feasible."
In 2018, Samsung and TSMC introduced ASML's 0.33 NA EUV scanner for manufacturing 7nm chips, most recently 5nm. ASML's EUV scanner supports 13nm resolution and throughput of 135 to 145 wafers per hour (wph).
But the EUV isn't perfect. The process can sometimes lead to unnecessary changes and defects. System uptime is also an issue.
Still, at 7nm, chipmakers are using UV to pattern chip features, with spacing starting at 40nm. Vendors are using a single patterning method based on EUV. The idea is to place chip features on a mask and then print them on the wafer using a single lithography exposure.
Chipmakers want to expand the EUV single pattern as much as possible. The EUV single composition reaches the limit at a distance of 32nm to 30nm, representing about 5nm nodes.
At these pitches and above, roughly at the 3nm node, chipmakers need to look for a new option, namely the EUV dual pattern. In double patterning, you split the chip features on two masks and print them on the wafer. It's complicated and expensive, but it's also something fabs have mastered with 193nm lithography.
Some people may want to avoid EUV double patterns altogether. "Now we are approaching the limit of a single exposure of 0.33 NA EUV, and for this we are considering High NA EUV," Arnaud Dauendorffer, a process engineer from TEL, said in a recent presentation at the SPIE Photomask Technology + EUV conference.
To avoid double patterning of UV, chipmakers are pushing for high-value aperture EUV of 3nm and above. The High-NA EUV promises a simpler single-pattern approach.
"The tool offers a higher resolution. This means that you can print more features with it. Aerial image contrast enables better local CD uniformity," said Jan van Schoot, Director of Systems Engineering at ASML, in a presentation at the conference.
ASML's first high numerical aperture EUV system EXE:5000 with 8nm resolution and 150 wph throughput. Customer shipments are scheduled for 2023. Then, at the end of 2024, ASML will ship a new version of EXE:5200 with a throughput of 220 wph.
The High-NA EUV works similarly to today's EUV lithography, but with some key differences. Unlike traditional lenses, the High Value Aperture tool includes an anamorphic lens that supports 8x magnification in one direction and 4x magnification in the other. So the field size was reduced by half. In some cases, chipmakers process one chip on two masks. The masks are then stitched together and printed on the wafer, which is a complex process.
New mask
The High-NA EUV also requires a new type of photomask. EUV is different from traditional optical masks. Optical masks consist of opaque chromium layers on a glass substrate, which allows them to transmit light.
There are several types of optical masks, such as binary masks and phase shift masks (PSMs).
Figure 2: Schematic of the various types of masks: (a) conventional (binary) masks; Source: Wikipedia
In a binary mask, chromium is etched at the selected location, exposing the glass substrate. The chromium material is not etched elsewhere. During operation, light hits the mask and passes through the area with glass, exposing the silicon wafer. Light does not pass through the chrome-plated area.
PSM is also used today. "There are many kinds of PSMs, but they work by using phase to cancel out unwanted light, resulting in images with higher contrast," says Chris Mack, CTO of Fractilia.
Today's EUV masks are binary and reflective. The EUV mask and/or blank consists of 40 to 50 alternating thin layers of silicon and molybdenum on the substrate. This results in multilayer stacks from 250 nanometers to 350 nanometers thick. On the stack, there is a ruthenium-based overlay, followed by a tantalum-based absorber.
Figure 3: Cross-section of an EUV mask.
In mask production, the first step is to create a substrate or mask blank. Manufactured by the mask blank supplier, the blank is used as the basic structure of the mask.
To manufacture EUV mask blanks, suppliers deposit alternating layers of silicon and molybdenum onto the substrate. Use actiographic and optical inspection equipment to check for defects in the mask blank.
Lasertec sells actinic blank inspection (ABI) systems for EUV mask blanks. The ABI tool uses a 13.5 nm wavelength with a sensitivity of 1 nm (height) x 40 nm (width) and a defect localization accuracy of 20 nm.
For high numerical aperture UV, Lasertec is developing a new ABI system with 1nm x 30nm sensitivity. "Our goal is 10nm of defect location," Masashi Sunako, president of Lasertec USA, said in a speech at the conference.
On top of that, the industry is developing new EUV mask types for 3nm and above. In today's EUV masks, the absorber is a 3D-like feature that protrudes from the top of the mask. During operation, EUV light illuminates the mask at an angle of 6°. Reflections may cause shadow effects on silicon or imaging aberrations caused by photomasks. This issue, known as the mask 3D effect, causes unnecessary pattern placement shifts.
To mitigate these effects, EUV masks require thinner absorbents. In existing EUV masks, the tantalum absorber is 60 nm thick. It can be made thinner, but limited to 50 nm, which does not solve the masking effect. In response, the industry is developing several new EUV mask types, such as 2D, absorberless, high k, non-reflective, and PSM.
The EUV PSM seems to have the most momentum. This technology solves the masking 3D effect while also improving image quality with better contrast.
But the EUV PSM may require a different material.
In a presentation at the SPIE Photomask/EUV conference, researchers at Hanyang University described a phase-shifted EUV mask consisting of alternating layers of ruthenium and silicon on a substrate. The ruthenium overlay is located at the top of the multilayer structure, followed by the tantalum-boron etched stop layer, and the ruthenium alloy as a phase-shifting material.
In a paper, Hoya developed various attenuated phase-shifted absorbers and evaluated their performance. "PSM expects to bring imaging gains," Ikuya Fukasawa from Hoya said in a talk. "But in order to develop EUV PSM blanks, we had to meet a lot of requirements. The absorbent material must have a small roughness and high durability to mask cleaning. Of course, the absorber must be etched in the mask process. ”
Like the EUV PSM, the High k mask is under development. High k EUV masks are similar to today's EUV masks. The industry is exploring other materials such as nickel, rather than tantalum absorbers. Thinner nickel absorbers can mitigate the masking effect, but this material is difficult to use.
Meanwhile, startup Astrileux recently described a new non-reflective EUV mask using ruthenium materials. Supriya Jaiswal, CEO of Astrileux, said: "Our masks are darker in dark areas, brighter in clear areas, and have less overall background lighting and leakage. ”
Astrileux also describes a 2D mask in which an absorber is combined in a blank. The startup also talked about aless flowon masking. All of this is in development.
For now, chipmakers will continue to use existing EUV mask/blank structures for existing 0.33 NA EUV tools. Then at some point the chip manufacturer may insert an EUV PSM for the 0.33 EUV. When a high-value aperture EUV is ready, chipmakers may use PSM. High k and other mask types are also possible.
Geoff Akiki, President of Hoya LSI at Hoya Group, says, "As you grow, there are several methods, whether it's phase shift, low n or high k. "The real trick here is to integrate and make it work in manufacturing, roll it out as a product." For example, you have things like flatness that we spend a lot of time worrying about. You have flaws, we're all talking about. In a sense, the choice of all these things is like trying to adjust a process window. That's what makes you end up with something available, not under ideal conditions. ”
New masking equipment
At the same time, once the mask blank is made, it is shipped to the photomask supplier. At the mask supplier, browns are patterned, etched, repaired and inspected. Finally, the film is mounted on the mask.
Figure 4: EUV mask manufacturing steps. Source: Simatai
First, photomask manufacturers use a system called an electron beam mask writer to write patterns on the mask based on a given IC design. For many years, mask manufacturers relied on single-beam electron beam tools based on Variable Shape Beam (VSB) technology. In operation, the mask is inserted into the system and the electrons hit the mask in the form of a shot.
THE VSB-based mask writer is suitable for traditional optical masks. But the EUV mask has smaller, more complex features, and the VSB is too slow to pattern it.
For UV and some complex optical masks, mask manufacturers use multi-beam mask writers. IMS Nanofabrication's multi-beam mask writing tool accelerates the process with 262,000 tiny beams. The write time is constant, and it takes about 12 hours to pattern all masks.
IMS is rolling out its second-generation tools, which include a new R&D version. "For high numerical aperture EUV mask manufacturing, the new MBMW-301 tool will be equipped with more beams," said Hans Loeschner, senior consultant at IMS.
NuFlare is also developing a multi-beam mask writer. These systems are designed to pattern the next generation of EUV and curve masks. The industry is also developing curved shapes on advanced photomasks using reverse lithography (ILT). So-called ILT masks will become important for UV, especially high NA.
"ILT masking is a way to enhance the process window to improve the resilience of the wafer production process to manufacturing changes," says Fujimura of D2S.
After the patterning step, the mask structure is etched and cleaned, forming a photomask. During the production process, defects may appear on the photomask.
This can be problematic. Because during lithography, the light from the scanner passes through the photomask, projecting the desired image onto the silicon wafer. If the mask is defective, irregularities may be printed on the wafer. This will affect the yield of the die and even destroy a chip.
Therefore, during the mask making process, it is necessary to check whether the photomask is defective. For traditional optical masks, photomask manufacturers use optical mask detection systems. Applied Materials, KLA, Lasertec, and NuFlare sell these systems.
Optical inspection tools can also detect EUV masks. The problem with optics is resolution. They may lose power at half-pitch resolutions of 20 nanometers to 16 nanometers.
In response, Lasertec recently introduced an actinic pattern mask detection (APMI) system using a 13.5 nm light source. The small wavelength allows the system to locate sub-20nm defects in the EUV mask.
Lasertec is also developing APMI systems for high numerical aperture EUV masks. "The new optics, detectors and system designs have been completed," says Lasertec's Sunako. The tool is scheduled to be available in 2023/2024.
In addition to optics and APMI, customers have another option for EUV mask detection. That's when KLA and NuFlare are developing multi-beam electron beam mask detection tools.
NuFlare is developing a multi-beam inspection system with 100 beams, scheduled for launch in 2023. "The sensitivity is 15 nanometers. The inspection time is 6 hours per mask inspection cycle," said Tadayuki Sugimori of NuFlare.
All in all, for current and future EUV masks, photomask manufacturers will use all detection types – actinic, electron beam, and optical.
As with inspections, mask repair is critical. If the masks are defective, the photomask manufacturer can repair them using a mask repair system. There are two types of mask repair tools, electron beams and nanofabrication. The two are complementary.
For advanced nodes, ZEISS has introduced a new mask repair tool using electron beam technology. The system repairs masks and defects with half spacing as low as 60 nanometers on extruded parts of 10 nanometers and smaller sizes.
At the same time, Bruker offers mask repair tools using nanofabrication technology. These systems contain a tiny tip to repair mask defects.
All mask repair tools must keep up with the scaled-in features and defect sizes of advanced nodes. They also have to deal with a variety of materials. "Material independence for these processes is critical to removing drops and other residual soft defect contamination, as material properties are often unknown," said Jeff LeClaire, Bruker's technical director.
New photoresist is required
Photoresists are also important for lithography. Chip manufacturers need photoresists with good resolution [R], low line width roughness [L], and sensitivity [S].
The industry has developed photoresists for lithography. But for the EUV, the situation is different. This is largely due to the difficulty of getting all three of these parameters at the same time because they are interrelated, and improvements in one parameter usually reduce at least one of the other parameters – often referred to as the RLS trade-off.
The EUV photoresist in production is based on two technologies – chemically amplified resists (CAR) and metal oxides. CAR for optics and UV involves a complex process. When photons hit the photoresist in the scanner, it causes a chain reaction.
"Part of the reaction cascade involves the chemical amplification of the initial photons, in which the photons are first converted into several electrons, and each incident photon eventually produces several photoacid molecules. The advantage of CAR is that the sensitivity of the photoresist can be improved by increasing the number of photoacid molecules produced by each photon. However, these extra acids will move farther and farther away from where the original photons are, resulting in blurred images, which reduces resolution and increases line edge roughness.
Metal oxide photoresists are less mature, but they have some advantages. For example, Inpria's metal oxide photoresist is based on a tin oxide structure that captures EUV photons more efficiently.
Today, the industry is looking for a photoresist that meets the RLS requirements of high numerical aperture UV. This is still an ongoing work. Researchers at the Paul Scherrer Institute (PSI) and ASML are using interfering EUV lithography systems to screen for a variety of resistants with high NA. The researchers patterned lines and spaces with a variety of resists, hoping to achieve 8nm half-pitch resolution.
PSI recently demonstrated results from UNLISTed CAR and non-CAR resists. Using a CAR dose of approximately 60mJ/cm, PSI's R&D EUV system creates clear lines and spatial patterns at 13nm half-spacing, but encounters slight bridging at 12nm and pattern collapse at 11nm. Timothée Allenet, a researcher at PSI, said in a speech: "We have increased the final resolution of chemically amplified resists from 12 nanometers to 11 nanometers, simply by optimizing the underlying layer. ”
Meanwhile, according to PSI, molecular photoresists exhibit good images at 13 nm at a dose of 30 mJ/cm, but they experience a malfunction due to pattern collapse at 12 nm.
Then, using different doses, metal oxide photoresists show good results down to 12 nm. "At 11nm half-pitch, we had a slight bridging and then a resolution bottleneck at 10nm," Allenet says.
On the bright side, the resistance of today's 0.33 NA EUV has not stalled and is improving. Tel, for example, describes new processes for CAR and metal oxide resists.
"All in all, the coater/developer process, together with the optimized underlying film, shows an improvement in the CAR pattern collapse margin. The optimized underlying layer improves the defect density, yield and roughness of the metal oxide resist," says Tel's Kanzo Kato.
conclusion
Other EUV technologies are also being developed, such as thin films. The film is used to cover the mask and prevent particles from falling on the mask.
ASML has developed a new EUV film. Meanwhile, Imec's carbon nanotube film showed 97.7 percent transmittance on ASML's EUV scanner. Both single-walled and multi-walled films are promising.
"Both types perform well, with little difference in imaging compared to unprotected film references in CD uniformity, LWR, and flares. Based on the measured EUV absorption of these films ranging from 95.3% to 97.7%, a slight increase in the dose is expected," said Emily Gallagher, a key member of the Imec technician.
There is no doubt that many people are developing other technologies for high-value aperture UV. Regardless of whether all the parts are in place, chipmakers say that chip production in 2023 and beyond will require high-value aperture UV.
Still, R&D costs are just beginning to pile up. Not many people can afford these systems. In addition, it remains to be seen when the High NA lithography machine will actually go into production.
Copyright information: This article is quoted from semiconductor industry observation, the copyright belongs to the original author, and the article is only used for academic sharing.