0 Introduction
For more than 20 years, silicon carbide (SiC) has received increasing attention as a wide bandgap power device [1]. Compared with silicon, silicon carbide has many advantages, such as: silicon carbide band gap is larger, which makes the silicon carbide device has a lower leakage current and higher operating temperature, anti-radiation ability is improved; silicon carbide material breakdown electric field is 10 times that of silicon, therefore, its device can be designed with higher doping concentration and thinner epitaxial thickness, compared with the same voltage level of silicon power devices, lower on resistance; silicon carbide has the characteristics of high electron saturation rate, so that the device can operate at a higher switching frequency; at the same time, The higher thermal conductivity of the silicon carbide material also helps to increase the overall power density of the system. The characteristics of high frequency, high voltage, high temperature resistance, fast switching speed and low loss of silicon carbide devices make the efficiency and power density of power electronic systems move in a higher direction.
These excellent characteristics of silicon carbide devices need to be fully demonstrated by the efficient and reliable connection of power and signal through packaging and circuit systems, and the existing traditional packaging technology is faced with some key challenges when applied to silicon carbide devices.
Silicon carbide devices have a smaller junction capacitance and a low gate charge, so switching speeds are extremely fast, with both dv/dt and di/dt during switching. Although the switching losses of the device are significantly reduced, the stray inductance parameters in conventional packages are larger, which produces greater voltage overshoot and oscillation at very high di/dt, causing device voltage stress, increased losses, and electromagnetic interference problems [2-3]. In the case of the same stray capacitance, higher dv/dt also increases the common mode current. In view of the above problems, scholars at home and abroad have researched and developed a series of new packaging structures for reducing stray parameters, especially to reduce stray inductance.
In addition to faster switching speeds, SIC devices can operate at temperatures above 300°C [4]. The existing traditional packaging materials and structures suitable for silicon devices generally work below 150 °C, and the reliability at higher temperatures drops sharply, or even fails to operate normally. The key to solving this problem is to find the right connection material for high temperature operation and match the thermal properties of different materials in the package. In addition, versatile integrated packaging technology and advanced thermal dissipation technology also play a key role in increasing power density [5].
This paper focuses on the three key technical directions of low spurious inductance packaging, high temperature packaging and multifunction integrated packaging to sort out and summarize the packaging of existing SILICON carbide power devices, and analyze and explore the challenges and opportunities faced.
1 Low spurious inductance packaging technology
Most of the existing commercial SiC devices are still packaged in the traditional Si devices, as shown in Figure 1. This method first solders the back of the chip to the substrate through solder, then leads out the front electrode through the metal bonding line, and finally plasticizes or fills the rubber. Traditional packaging technology is mature, low cost, and compatible with and replaces legacy Si-based devices.
However, the traditional package structure leads to a large stray inductance parameter, which causes serious voltage overshoot during the rapid switching process of silicon carbide devices, and also leads to problems such as increased losses and electromagnetic interference. The size of the stray inductor is related to the area of the switching converter circuit. Among them, the metal bonding connection method, component pins and the plan layout of multiple chips are the key influencing factors that cause the traditional package commutation loop area to be large.
Table 1 lists and classifies typical SIC device package structures, as well as the stray inductance parameter sizes for the relevant package method. As can be seen from Table 1, eliminating the metal bonding lines effectively reduces the stray inductance value and keeps its size below 5nH. The typical packaging structures are described below.
1.1 Single tube flip chip package
The University of Arkansas team[6] drew on BGA's packaging technology to propose a single-tube flip-chip packaging technique, as shown in Figure 2. The package flips the back electrode of the chip to the same planar position as the front electrode through a metal connector, and then implants a solder ball at the corresponding electrode position, eliminating the metal bonding wires and pin terminals. Compared to the TO-247 package, the volume is reduced by a factor of 14 and the on-resistance is reduced by 24%.
1.2 DBC+PCB hybrid package
The direct bonded copper-DBC used in traditional module packages limits the chip to a two-dimensional plane layout, with a large current loop area and large stray inductance parameters. CPES, Huazhong University of Science and Technology [7-9] and other teams combined the DBC process with the PCB board, using metal bonding wires to connect the upper surface of the chip to the PCB board, controlling the converter loop between the PCB layers, greatly reducing the current loop area, and then reducing the stray inductance parameters. As shown in Figure 3, the hybrid package can control stray inductors below 5nH and reduce the volume by 40% compared to conventional modules [9-10].
Flexible PCB boards combined with sintered silver process are also used in commercial modules. Figure 4 shows Semikron's 1200V/400A SiC module using SKiN packaging technology[11]. This technology uses a flexible PCB board instead of bonding wire to achieve the upper and lower surface electrical connection of the chip, the internal loop parasitic inductance of the module is only 1.5nH, the switching speed is greater than 50kV/s, and the loss can be reduced by 50% compared with the traditional module.
Combining the advantages of 2 proven processes, this hybrid package is easy to manufacture, allowing for low stray inductance and smaller volumes. However, the existence of PCB boards limits the reliability of the above packaging methods to operate at high temperatures.
1.3 Chip front plane interconnect package
In addition to using a flexible PCB board instead of a metal bonding wire, a planar interconnect connection method can also be used to achieve a connection on the front of the chip. Figure 5 shows Silicon Power's direct lead bonding (DLB) soldering method,[12] similar to IR's Cu-Clip IGBT[13] and Siemens' SiPLIT technology[14]. Planar interconnects not only reduce current loops, which in turn reduce stray inductance and resistance, but also have better temperature cycling characteristics and reliability.[12]
The buried package for SiC chips [15-17] can also be considered a flat, direct-attach package on the front of the chip. As shown in Figure 6 [17], this method places the chip in a ceramic positioning slot, fills the gap with an insulating medium, and finally covers both sides of the mask with sputtering metal copper to achieve electrode connection. By selecting a reasonable packaging material, the interlayer thermal stress of the module at high temperatures is reduced, and the forward and reverse characteristics of the module can be measured at a high temperature of 279°C.
The planar direct-attached packaging process expands the current loop from the planar layout of the DBC board to the interlayer layout of the upper and lower planes of the chip by eliminating the metal bonding line, significantly reducing the loop area and achieving low stray inductance parameters, which is the same as the basic idea of achieving low stray inductance in the double-sided thermal package and the three-dimensional package introduced later, but the implementation method is slightly different.
1.4 Double-sided thermal packaging technology
The double-sided packaging process is more commonly used in packaging applications of IGBTs inside electric vehicles due to its double-sided heat dissipation and small size [18-21]. Figure 7 shows a typical double-sided thermally packaged SiC module[22] with both the upper and lower surfaces soldered using a DBC board, so that both the upper and lower surfaces can dissipate heat at the same time.
The difficulty of this process is that the surface of the chip needs to be sputtered or plating to make it solderable, and metal gaskets, connecting columns, etc. are added to the surface of the chip to eliminate the height difference between the different heights of the chips in the same module. Coupled with the fact that the SiC chip is generally small in area, how to ensure the quality of the weld within the limited area of the upper surface is the key to the process. Thanks to symmetrical wiring and a reasonable chip layout of the upper and lower DBCs, the package reduces loop parasitic inductance parameters below 3nH,[23] reducing the module thermal resistance by 38% compared to conventional packages.[24] Domestic teams such as Zhuzhou CRRC Times Electric and Tianjin University have conducted research on such double-sided packaging modules in many aspects such as heat[21], electrical, and reliability[25].
CPES's SiC MOSFETs for 10kV use the package design shown in Figure 8 [26]. The chip is connected to the direct bonded aluminum (DBA) and molybdenum sheet using silver sintering technology. Among them, the lower part of the chip adopts two layers of DBA board superposition, and the middle layer is connected to the middle voltage of the busbar, which can reduce the field strength of the edge of the board on the one hand, and reduce the parasitic capacitance of the point to ground in the middle of the bridge arm on the other hand, reducing EMI. The module can use double-sided heat dissipation or solder the porcelain capacitor to the upper DBA board of the chip, reducing the loop parasitic electrical sensation to less than 5nH.
Figure 9 shows a double-sided crimp module for SiC MOSFETs proposed by Zhejiang University and the University of Arkansas[27]. The module uses a low-temperature co-fired ceramic (LTCC) process and an elastic Fuzz Button instead of traditional DBC boards and metal bonding wires for chip interconnecting and thermal design, with a loop parasitic inductance parameter of only 4.3nH. The disadvantages are the LTCC's low thermal conductivity and the characteristics of the crimp modules that react sensitively to external pressures. In addition, the screw-fastened double-sided crimp SiC MOSFET module, designed by Zhejiang University in collaboration with the University of Alberg, also achieves low parasitic inductance parameters and good uniform heat dissipation characteristics [28].
1.5 Three-dimensional (3D) packaging technology
The 3D packaging technology takes advantage of the vertical structure of the SiC power device to stack the down tube of the switch arm directly on top of the upper tube, eliminating redundant wiring at the midpoint of the bridge arm and reducing the loop parasitic inductance below 1nH [29-31]. Vagnon proposed a direct-to-metal module unit in 2008, as shown in Figure 10(a),[29] and built a Buck converter module based on this package. Experimental tests have shown that the common source electrode inductance is basically eliminated in the 3D package module, and the radiated electromagnetic field is greatly reduced compared to the traditional module, and the common mode current is also well suppressed [30]. Similarly, the document [32] embeds a SiC MOSFET chip inside the PCB to form the 3D package as shown in Figure 10(b). The surface of the chip is first plated with copper, and then the electrodes of the chip are drawn out by the via copper immersion process, and finally the multilayer structure is completed by PCB lamination, Figure 10(c) is the physical module. Thanks to the motherboard structure of the PCB, the module loop inductance is only 0.25nH and the Kelvin connection of the gate can be implemented at the same time. The power density of the package is extremely high, how to ensure the temperature control of the chip is a major difficulty, the outer copper thickness and the surface thermal convection coefficient have a great impact on the heat dissipation of the chip. In addition to power chips, passive components such as magnetic cores, capacitors, etc. can be embedded in the PCB in an appropriate manner to increase power density [33-34].
As can be seen from the above new structure, in order to give full play to the advantages of SiC devices, it is a trend to increase power density and eliminate metal bonding wire connections. By adopting various new structures, reducing the parasitic inductance value of the module loop and reducing the volume is the guarantee of promoting power electronics to high frequency, high efficiency and high power density.
2 High temperature packaging technology
Copper wire can be used instead of aluminum wire for the frontal connection of the chip, eliminating the difference in coefficient of thermal expansion between the bonding wire and the DBC copper layer, greatly improving the reliability of module operation.[35] In addition, the aluminum and copper strip connection processes are expected to provide a better solution for silicon carbide due to their greater interception capacity, better power cycling, and heat dissipation capabilities [36-37]. Figure 11 shows the copper bonding wire and copper belt connection method, respectively.
Solder sheet or solder paste is often used in the connection of chips and DBC boards, soldering technology is very mature and simple, by adjusting the proportion of solder components, improving solder paste printing technology, vacuum soldering to reduce the void rate, adding reducing gas and so on can achieve extremely high quality welding process. However, the low thermal conductivity of the solder (~50W/(m K)) and the fact that it will vary with temperature are not suitable for SiC devices to operate at high temperatures. In addition, the reliability of the solder layer is also a major cause of module failure.
Sintered silver connection technology is expected to replace solder as a new connection method for SiC devices due to its extremely high thermal conductivity (~200W/(m K)), low sintering temperature, and high melting point. The silver sintering process is usually to mix silver powder with organic solvents into silver solder paste, then print it onto the substrate, remove the organic solvent by preheating, and then pressurize the sintering to achieve the connection between the chip and the substrate. In order to reduce the sintering temperature, one method is to increase the pressure applied in the sintering, which increases the corresponding equipment cost, and it is easy to cause chip damage; the other method is to reduce the volume of silver particles such as the use of nano-silver particles, but the processing cost of the particles is high, so many studies continue to study micron silver particles to obtain suitable sintering temperature, pressure, and time parameters to present a more ideal sintering effect [40]. Figure 12 shows some typical thermal conductivity and operating temperature comparisons of solder and sintered materials [39].
In addition, in order to ensure the stable operation of silicon carbide devices, ceramic substrates and metal substrates also need to have good high-temperature reliability. Tables 2 and 3 give some commonly used substrate insulation materials and baseplate materials [40], where λ is the thermal conductivity, α is the coefficient of thermal expansion, R is the flexural strength, and ρ is the density. The higher the λ, the better the heat dissipation effect, and the α affects the thermal stress between different layers of materials when the package is working at high temperature, and the greater the difference in α between different materials, the higher the thermal stress between the layers of the material, and the lower the reliability. Therefore, finding materials with high lambda, α values and similar sicide materials (3.7ppm/K) is the key to improving packaging reliability.
As shown in Table 2, Al2O3 has the advantages of low cost and high mechanical strength, and is the most commonly used insulation material at present, but the lambda value is low, the α value is obviously large, and it is not suitable for high-temperature work of silicon carbide. The high AlN λ value, the α value is close to the SiC material, the cost is suitable, and it is currently the ideal substrate material for silicon carbide devices. Although BeO has a high lambda value, its strong toxicity limits its application. Si3N4 α value is the closest to SiC material, and the large R value, less likely to break in the thermal cycle, is also an insulating material suitable for high temperature operation of silicon carbide devices, but its low lambda value and high cost limit its wide range of applications.
In order to improve the reliability of the copper clad layer of ceramic substrates, processes such as aluminum-clad ceramic plates (DBAs) and active metal brazing (AMB) have also attracted more and more attention. As shown in Table 3, Cu has the highest thermal conductivity as a baseplate material, but the coefficient of thermal expansion between it and the substrate is quite different. Al, as a baseplate, is low cost and significantly reduces overall weight, but is poor in terms of thermal conductivity and coefficient of thermal expansion. Cu-based alloys such as Cu/Mo, Cu/W, Cu/C, etc. have superior performance in terms of thermal conductivity and coefficient of thermal expansion, but their density and cost are higher. The cost, density, and coefficient of thermal expansion of AlSiC are ideal, but the disadvantage is that the thermal conductivity is low.
The specific use needs to be comprehensively decided in light of the actual situation. In summary, it can be seen that the material is the basis for ensuring the reliable operation of silicon carbide devices at high temperatures. In the actual design process, considering various comprehensive factors to find the most suitable material is also a major difficulty in the design of device packaging.
3 Versatile integrated packaging technology
3.1 Multifunctional integrated packaging technology
The emergence of silicon carbide devices has promoted the development of power electronics in the direction of miniaturization, and the trend of integration is becoming increasingly obvious.
The integration of porcelain capacitors is more common [41], and the parasitic inductance parameters of the power loop can be effectively reduced by placing the porcelain capacitor as close as possible to the power chip, and the oscillation and overshoot phenomenon during the switching process can be reduced. However, at present, the porcelain capacitor is not resistant to high temperature, so it is not suitable for the high temperature operation of silicon carbide.
Mitsubishi, Infineon and other companies have proposed SiC intelligent power module (IPM), the drive chip and related protection circuits integrated into the module, and used in home appliances and other equipment [42-43]. As shown in Figure 13, the Zhejiang University team greatly reduced the parasitic inductance parameters of the drive loop and power loop by integrating the porcelain chip capacitor, driver chip, and 1200V SiC power chip on the same DBC board, so that the area of the half-bridge module was only the size of a TO-247 single tube[44]. The University of Arkansas developed SiC CMOS driver chips for silicon carbide chips to fully exploit the high-temperature performance of SiCs.[45]
In addition, EMI filter integration, temperature and current sensor integration, and microchannel heat dissipation integration are used in the design of silicon carbide packages [5].
3.2 Heat dissipation technology
Heat dissipation technology is also a major focus and difficulty in the design of power electronic systems. In the design, a single tube or module is usually attached to the radiator and then dissipated by air cooling or liquid cooling. In the literature [46], the micropath is integrated into the substrate of the module, which reduces the overall thermal resistance of the module by 34%. Microchannel heat dissipation technology is also used for direct heat dissipation of chips, for example, in the literature [47] three typical ways for wide bandgap devices are described: one is to make micropaths directly on the substrate of the chip; the second is to integrate the micropaths in the thick metal layer of the lower layer of the chip; and the third is to connect the chip directly to the Si-based microchannel structure through metal plating and hot media materials. This heat dissipation technology that directly acts on the chip eliminates the limitation of the multi-layer structure of the module, and can greatly improve the heat dissipation efficiency of the chip. Phase change heat dissipation technologies such as heat pipes and sprays have higher thermal conductivity than single-phase gas cooling and water cooling, which is very efficient and provides a solution for the heat dissipation of SiC devices [48]. Figure 14 shows a simple comparison of the heat transfer coefficients between current heat dissipation methods [39].
4 Challenging opportunities and prospects
As power electronics move towards efficient, high-power density, the device's low spurious parameters, high-temperature packaging, and versatile integrated packaging play a key role. Achieving low stray inductance by reducing the area of the high-frequency switching current loop is a technological trend in silicon carbide packaging. However, achieving a breakthrough in SIC encapsulation technology and applying it on a large scale will require a lot of work, and here are some of the core challenges and prospects:
1) Further study and verification of the comprehensive performance of low stray inductance package structure. For example, the power cycle and temperature cycle capability of the package structure, the actual heat dissipation effect, the manufacturing difficulty and cost, and the difficulty of realizing the series parallel connection of high-power modules.
2) Research on encapsulation materials suitable for high temperature operation. The development of high-temperature resistant, excellent thermal conductivity, thermal expansion coefficient matching packaging materials is always the key to improving the reliability of high-temperature packaging work, at the same time, improving the process, reducing the production cost and process difficulty of existing excellent packaging materials are also important constraints on the development of packaging in the direction of high temperature.
3) Multifunctional integrated package module internal interference, common heat dissipation and other key issues research. The multi-functional integration of modules is the development trend of power electronics, but the ceramic chip capacitors, sensors, gate drives, etc. cannot fully match the high-temperature and high-frequency performance, heat dissipation and electromagnetic compatibility problems of silicon carbide; the development of high-temperature capacitors, the integration of sensors in the power chip chip, the study of SiC CMOS driver chips or the use of SOI (silicon on insulator) and other process solutions need to be further explored.
4) Exploration of new heat dissipation methods. Reducing the thermal resistance on the chip heat dissipation path is the key to the package heat dissipation technology, on the one hand, the use of high thermal conductivity materials, on the other hand, can reduce the lamination structure of the package, such as: DBC direct heat sink, micro channel liquid cooled heat sink integration and chip direct heat dissipation method are the heat dissipation of silicon carbide devices to provide more possibilities.
It is foreseeable that the development of silicon carbide devices and packaging technologies has opened a broader door for power electronics technology, helping power electronics technology to move forward in the direction of high frequency, high efficiency and high power density.
5 Conclusion
This paper analyzes and discusses 3 key technical issues in the silicon carbide device packaging: 1) summarizes the new package structure with low stray inductance parameters, summarizes its basic ideas from the design principle and lists some typical package structures; 2) summarizes some of the commonly used high-temperature packaging methods and material characteristics, and points out the key problems and solution ideas in high-temperature packaging; 3) summarizes the existing trend of multi-functional integration of silicon carbide packaging and heat dissipation technology. Finally, the packaging technology of silicon carbide is envisioned, pointing out the challenges and opportunities it faces.
Source: Proceedings of the China Journal of Electrical Engineering Vol. 39 No. 19 Author: School of Electrical Engineering, Zhejiang University Sheng, Dong Zezheng, Wu Xinke