It is reported that Intel may once again focus on the study of transistor design to accelerate the emergence of chip process processes of 2nm and below.
Recently, a patent that has been passed shows that Intel has developed a "Stacked Forksheet Transistors".
It is understood that the patent application was filed by Intel's component research group, which indicates its interest in developing chips that are faster and more effective with the same power.
In addition, the stacked forkboard transistors developed by Intel can achieve a vertically stacked 3D CMOS structure.
The design is described as a transistor device made using a vertical semiconductor channel stacked near the edge of the trunk, with the second transistor stacked on top of the first transistor, and the second transistor similarly stacked with vertical semiconductor channels adjacent to the trunk.
Figure | Perspective description of stacked fork plate transistors (Source: U.S. Patent Database FPO)
However, sufficient technical details are not visible from the patent documents, and Intel has not actually submitted referenceable PPA (power, performance and area) improvement data.
It is known that the stacked fork plate transistors are mainly a combination of nanostrip transistors and germanium atomic films for application. Among them, the germanium atom film acts as a dielectric wall (Dielectric Wall), which acts as a physical separation of the vertically stacked transistors, and is also an insulator between the p-gate groove and the n-gate groove.
Under this design architecture, nmOS (N-Metal-Oxide-Semiconductor) and PMOS (Positive Channel Metal Oxide Semiconductor, P-Type Metal-Oxide-Semiconductor) transistors will be more tightly arranged, leaving more space, but their respective functions will not be affected.
Stacked forkboard transistors are difficult to shrink compared to today's most advanced tri-gate transistors, but this design allows for an increase in the number of transistors.
With this stacked transistor technology, Intel can not only add more transistors to the chip, but also enable the chip to send signals in three dimensions rather than the two-dimensional technology currently used on chips to enable faster communication between transistors.
Back in 2019, Intel demonstrated the stacked transistor technology at the International Electron Devices Meeting (IEDM), when the technology was still in the development stage.
However, the company has not yet released data on transistor performance, density and efficiency of stacked forkboard technology.
In fact, Intel isn't the only company working on stacked forkboard technology.
In 2019, a team of researchers at the Interuniversity Microelectronics Centre (IMEC) posted online a document describing a transistor of a related technique, which they call a stacked fork plate transistor.
Compared to traditional transistor technology, IMEC's transistors have significantly improved transistor density when applied to the 2nm process chip process.
The data shows that at constant frequencies, the stacked forkboard transistors are 10% faster, 24% more efficient, and 20% less unit area. In addition, Static Random-Access Memory (SRAM), which is commonly used for on-chip caching, will reduce the footprint by 30 percent, one of the main "members" that occupy the total area of the chip.
This shows that at process nodes of 2nm and below, stacked forkboard transistor technology helps improve chip performance.
Intel and IMEC have been working together to establish a long-term and close relationship in nanoelectronics, and IMEC's previous research has become the basis for Intel's new patent.
It is important to note that not all patents that have been approved have the opportunity to become real products or manufacturing techniques.
Figure | Floor plan and cross-sectional view of a stacked forkboard transistor (Source: U.S. Patent Database FPO)
At this time, it is uncertain whether Intel will use stacked forkboard transistors in its 2nm process, and Intel has not made any claims or predictions about the performance of its proposed fork transistors.
However, since Intel filed a patent for this stacked forkboard transistor, it shows that it has some significance. After all, the company knows more about the viability of this technology than Volkswagen.
For decades, Intel has named chip process nodes in a way that adds digitally decreasing units of size such as nanometers, which refers to the distance between gates. Not long ago, the company changed this naming style to better reflect the transition to a new era.
It is reported that Intel will name the next node after Intel 3 Intel 20A and launch the process process in 2024. Where 20A is equivalent to 2nm, A stands for "Angstrom".
In addition to the new node naming, Intel said it will make breakthrough improvements to the 20A in two major areas.
In this process node, Intel will replace the original FinFET transistor technology with a new GAI RibbonFET (Gate-All-Around RibbonFET) transistor architecture and use PowerVia power supply technology.
In addition, Intel has also indicated that it will make some new improvements to the Intel 20A, which will drive the development of Intel 18A. Combined with Intel's new patent in transistor architecture, its new improvement to Intel 20A may be the application of stacked forkboard transistors.
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reference:
https://techxplore.com/news/2022-01-intel-stacked-forksheet-transistor-patent.html
https://www.freepatentsonline.com/20210407999.pdf