The JEDEC organization today officially released the standard specification for the new generation of high-bandwidth memory HBM3, numbered JESD238.
The HBM3 standard continues to expand and upgrade at all levels of storage density, bandwidth, channels, reliability, energy efficiency, etc., including:
- The transmission data rate doubles again on the basis of HBM2, with a transmission rate of 6.4Gbps per pin, with a width of 1024-bit, and the maximum bandwidth of a single pin can reach 819GB/s.
If you use four, the total bandwidth is 3.2TB/s, and six can reach 4.8TB/s.
- The number of independent channels has been doubled from 8 to 16, plus the pseudo channel, and each one supports 32 channels.
- Supports 4/8/12-high TSV silicon perforated stacks, which will be expanded to 16-high in the future – which can be understood as an internal stack of 4-16 pieces.
- Each storage tier has a capacity of 8/16/32Gb, starting at 4GB (8Gb 4-high) and a maximum capacity of 64GB (32Gb 16-high) per storage tier.
- Support platform-level RAS reliability, integrated ECC check and error correction, support real-time error reporting and transparency.
- Improved efficiency, the main interface uses 0.4V low swing modulation, and the operating voltage is reduced to 1.1V.
NVIDIA, SK Hynix, Micron, Synopsys and other companies have expressed their support for HBM3 memory for the first time.
As early as last August, SK Hynix released the first batch of HBM3 products in advance, with a single capacity of 16/24GB, 12-high stacking, and a bandwidth of 819GB/s in the early stage, and recently increased to 896GB/s.
SK Hynix started HBM3
HBM2e