After Samsung and TSMC, Intel has also begun to make efforts in the 2nm process.
Author | Home scale from the planet Magnesia
Recently, a patent on the Internet suggests that Intel may use "stacked fork chip" transistor technology to continue Moore's Law and use it in semiconductor processes with advanced processes of 2nm and below.
The full name of the patent is "stacked forksheet transistors" technology. The patent does not provide much detail, and Intel does not provide improved data on PPA (Power Performance Area) as a reference.
According to Intel, "This patent describes the use of nanostrip transistors and germanium films, the latter of which will act as dielectric barriers, repeating in each vertically stacked transistor layer, ultimately depending on how many transistors are stacked on top of each other." This new transistor design could eventually enable a 3D and vertically stacked CMOS architecture that allows for an increase in the number of transistors compared to the most advanced tri-gate transistors currently available. ”
In simple terms, the purpose of this new structure is to further shrink the transistors while minimizing feature size when stacking semiconductors. Under the new structure, the two transistors, PMOS and NMOS, will be more tightly packaged together without affecting their operation. If all goes well, the footprint of the underlying CMOS device is at least halved, making it easy to double the density of the integrated circuit. But as mentioned earlier, this new structure will face great challenges in terms of manufacturing complexity due to the lack of more details provided.
In recent years, in the face of the challenges of AMD and other competitors, Intel has also begun to make big moves, first launching a well-known 12th-generation Alder Lake processor, and then announcing a return to the chip manufacturing field. The launch of the new patent is also intended to gain something in the field of chip foundry.
In addition to Intel, TSMC and Samsung have made progress in the 2nm process, and both chip giants hope to replace the current mainstream FinFET process with nanosheet/nanowire (nanosheet/nanowire) transistor structures. From the transistor model, Intel's structure seems to be able to accommodate more transistors, but the design idea is actually similar - the semiconductor material is stacked like blocks.
But not all patents can become actual products or manufacturing technologies, and at present, Intel's patent is still too difficult to achieve.