Intel's announcement today is too rich in new product news, in addition to the 13-16th generation Core processor and new process, Xeon Xeon processor, Arc Sharp graphics card, Arctic Sound-M multimedia card, and a special "Falcon Shores" (Falcon Shores).
It is based on the x86 Xeon processor platform (socket interface compatible), and integrates Xe HPC GPUs for high-performance computing, flexibly equipped with the number of cores, combined with next-generation packaging, memory, and IO technology to form a powerful "APU".
Intel says this flexible architecture can meet all supercomputing load needs, bringing huge performance, efficiency gains, and simplifying GPU programming for large-scale intensive computing, AI training models.
Specifically, compared to today's levels, the energy consumption ratio can be increased by a factor of 5, the density of x86 computing can be increased by a factor of 5, and the memory capacity and density can be increased by a factor of 5.
Falcon Shores products will ship in 2024.
It is part of Intel's HPC-AI supercomputing strategy and one of the main steps towards achieving a ZettaFLOS (10 trillion billion) supercomputer by 2027, which requires a 1,000-fold increase in computing performance over the next five years, building on the current 10 billion billion computations.
It is reported that AMD also plans to integrate an Instinct GPU that supports high-performance computing in the Zen4 architecture of the Xiaolong processor, and the idea is the same.
In addition, Intel also announced that the Ponte Vecchio, a high-performance computing GPU for 10 billion computing, will ship as planned later this year, the first batch of Aurora supercomputers for the U.S. Department of Energy.
Intel claims that Ponte Vecchio meets industry-leading performance standards for complex financial services workloads and demonstrates 2.6 times better performance than market-leading solutions.
Ponte Vecchio will be the first product of Intel Xe HPC's high-performance computing architecture, integrating more than 100 billion transistors, using 5 different processes, and integrating up to 47 tiles, including compute units, Rambo cache units, Foveros packaging units, base units, HBM units, Xe link units, EMIB units, and so on.