Recently, the Intel research team released the latest research paper, showing a method of stacking transistors, which can increase the number of transistors per unit area chip by 30%-50%. The company said it will continue to accelerate the speed of chip shrinkage in the next decade.
According to Reuters, Intel is trying to regain the lead in producing the smallest and fastest chips, and while CEO Kissinger has laid out plans to regain the lead in 2025, the progress of the work announced by the company's research team at an international conference in San Francisco has given people a glimpse of Intel's competitive plans after 2025.
It is reported that one of the ways Intel integrates more computing power into chips is to add chip stacks or chiplets in three-dimensional space. In addition to increasing transistor density, another technique demonstrated by the research team could increase the number of connections between stacked chips by a factor of 10, meaning more complex chips can be stacked together.
Paul Fischer, head of Intel's component research division and senior principal engineer, said in an interview with Reuters: "By stacking the chips directly on top of each other, we have significantly saved area. "We're cutting the length of the interconnect and really saving energy, which not only improves cost efficiency, but also improves performance."
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