Source: Content compiled by Semiconductor Industry Watch (ID: icbank) from semiwiki, thanks.
Intel recently released an excellent video that provides a deep chronology of MOS transistor technology. The Evolution of Transistor Innovation is a five-minute audiovisual adventure that showcases Moore's Law spanning 50 years. Here's a summary of some of the highlights, along with some screenshots – the full video is definitely worth watching.
The speaker was Marisa Ahmed, a veteran with more than 16 years of Intel experience who is part of the Technical Leadership Marketing team. Marissa is responsible for developing technology marketing strategies and campaigns to support Intel's process, packaging, and manufacturing capabilities.
In 1971
The figure above established the baseline for MOS field-effect transistors, circa 1971.
(Note additional supplemental information provided by the transistor cross-section below—for example, the total number of transistors released; the number of metal layers used for process generation; the exposure wavelength of the lithography pattern; wafer size; and the associated Intel product family.) ）
Polycide and Salicide: 1979-81
As dennard scales the device gate length, the thin layer resistivity of the polysilicon gate material is increasing. Similarly, the transistor drain/source series resistance (Rs, Rd) is increasing. Due to the scaling of the S/D junction depth, the contact resistance (Rc) of the metal layer also increases. To address these problematic parasitic effects, a process innovation for the manufacture of silicides emerged. Refractory metals (e.g. titanium) are deposited at high temperatures and alloyed with exposed silicon. (Salicide is a composite term for "self-aligning silicide"—the deposited metal does not react with adjacent dielectric materials.) ）
STI：1995
During the transition from LoCoS (local oxidation of silicon) to shallow STI (shallow trench isolation), the device's galvanic isolation and surface topography underwent significant changes.
LoCoS is a process method in which field oxide isolation between devices is formed by patterning a hard mask on the device region and exposing the field to an oxidizing environment. Oxygen diffuses from high temperatures through the growth field oxide layer to silicon crystals at the oxide-substrate interface. The resulting oxide profile is a tapered ("bird's beak") surface morphology that is more suitable for metal travel between devices.
To facilitate further scaling, a new process for field oxide separation was introduced. STI leverages significant improvements in anisotropic dry etching techniques with near-vertical sidewalls and chemical vapor deposition of dielectric materials.
Aluminum到 Copper
A watershed (non-device) process improvement in the late 1990s was the transition from aluminum metallization to copper. Dennard scaling continues to achieve greater device currents and lower device capacitance. The hallmark of this era was a significant contribution from the transition from circuit delays dominated by gate fan-out loads to R*C interconnect delays from driving gate outputs to fan-outs. The need for interconnects with improved resistivity and robust electromigration requires a transition from Al to Cu.
At the same time as this material transformation, a major transformation of the interconnect pattern is required. Aluminium, as the main interconnect, involves fairly simple deposition, lithography and subtraction processes. Due to the chemical difficulties associated with dry etching of copper – such as corrosive gases, there are almost no volatile copper-based reaction products to pump out – a mosaic patterning method is required. The dielectric surrounding the metal is deposited, the trenches are etched in the dielectric (and the interlayer dielectric below for through-holes), and then the copper is deposited in the grooves by plating.
In addition to adding inlay processes to replace subtractive aluminium etching methods, it is also necessary to develop chemical mechanical polishing (CMP) process steps. The die with Cu deposited face down is placed on a polishing pad that rotates at a low speed. The rotating piston with higher RPM provides the appropriate downward force on the wafer (Newtons/cm**2) and introduces the slurry onto the pad. The slurry consists of a chemical solution and fine sand particles. The chemical is designed to selectively react with the material to be removed (in this case, copper), while mechanical polishing removes the results of the reaction. This produces an extremely flat surface topography. As shown in the figure above and in the figures that follow, CMP makes the number of metal layers available for interconnect scaling circuit density urgently need to increase.
Gate and gate oxide reinforcement
Device development encountered problems with the continuous scaling of gate oxide thickness. The effect of the input gate electric field on the device channel requires scaling the gate oxide capacitor: Cg ~ ((K*E0)/t), where K is the relative dielectric constant and t is the gate oxide thickness. As the gate oxide becomes thinner, the gate tunneling current through the device input increases. To increase Cg equivalently without reducing the thickness, an alternative high K dielectric material replaces SiO2 as a gate oxide.
Scaling traditional polycrystalline silicon gate materials results in higher resistivity and greater sensitivity to unevenness in polycrystalline silicon grain size, distribution, and impurity concentration. An alternative metal gate process step was introduced, replacing polysilicon as the gate material. (For more information on this rather difficult step, continue searching for the high-K metal gate "HKMG first gate vs. post gate" process; the term substitution in the figure above refers to the post-gate process.) )
FinFET：2011
Intel's aggressive adoption of a new transistor topology, FinFETs (also known as "tri-gate FETs") on 22nm process nodes, surprised the industry.
When the device is "turned off", the leakage current (sub-channel) between the source and drain poles of the traditional planar S/D channel topology becomes more and more serious. To reduce sub-threshold leakage, a device topology is required where the gate input provides greater static control of the channel. The vertical channel "fins" have input gates that pass through the sidewalls and tops. In the figure above, a single gate input passes through three parallel silicon fins—channel current flows through the vertical fins. The thickness of the fins is small enough that gate input electric field control significantly reduces sub-threshold leakage, providing longer battery life for laptops and mobile electronics.
Gate-All Around (GAA) Ribbon FET：2024 年 Intel 20A
To further improve electrostatic gate control of the channel, another major development in transistor topology is emerging to replace FinFETs. The ring gate configuration involves vertical stacking of electrically isolated silicon channels. The gate dielectric and gate input utilize an atomic layer deposition (ALD) process flow around all channel surfaces in the stack.
Intel will release its GAA Ribbon FET 20A process in 2024.
summary
The development of field-effect transistors over the past 50 years is quite impressive.
This evolution has been driven by the innovative ideas and hard work of R&D teams across the industry, who have expertise in process steps ranging from materials science to chemistry to optical lithography to physical deposition/etching. Incredibly, this progress will definitely not stop anytime soon.