Source: Content by Semiconductor Industry Watch (ID: icbank) original, author: Gong Jiajia, thank you.
Today, the chip design giant's high-end series of chips have been fighting in advanced processes of 7nm and below. Not only that, the advanced process has become the "gold-absorbing code" of foundry faucets such as TSMC. In 2021, TSMC's total revenue was NT$1,587.42 billion (about RMB365.83 billion), of which the combined revenue of 5 nanometers and 7 nanometers accounted for 50% of the total revenue, which can be said to carry half of TSMC's revenue.
However, with the increase in demand for high-performance computing, the war on chip process has gradually spread from 5nm to 3nm. The "gunshots" of the 3nm scramble have begun.
The "capacity struggle" of design companies
At present, the chip has come to the era of advanced process, in view of the fact that the foundry that can use advanced process is only TSMC and Samsung, and the chip design companies that need advanced process technology are Intel, Apple, Qualcomm, AMD, NVIDIA and so on, which are really in the situation of "more monks and less meat". For chip companies, the competition of chip technology is actually a competition of product performance, in order not to lose to opponents, chip companies have to start to stage a "capacity battle".
Judging from the 5nm that has already been mass-produced, the industry rumored that Nvidia paid $1.64 billion to TSMC last quarter to retain its share of the 5nm, and another $1.79 billion will be paid in the first quarter of 2022. It is reported that Nvidia will spend nearly $10 billion to ensure that it provides 5nm chips for the RTX 4080, 4090 and 40 series.
For a mass production of nearly 2 years, can be called a stable yield of the process, Nvidia to spend tens of billions of dollars to ensure production capacity, it is conceivable that in the face of a new process, the competition of manufacturers will only be more intense, which determines who will be the world's first 3-nanometer chip.
At present, Intel, Apple, Qualcomm, AMD, etc. have all joined the battle.
Intel
Although Intel is an IDM company, he is still far from 3nm in terms of advanced processes. At the 2022 Investor Conference, Intel said that intel 4 or 7nm is expected to be put into production in the second half of 2022; Intel 3 (second generation 7nm) is expected to be put into production in the second half of 2023; Intel 20A (5nm) will be put into production in 2024; and Intel 18A (second generation 5nm) is expected to be put into production in 2025.
In other words, Intel's 3nm is still far away, but the technology competition will not give Intel a breathing time, after intel can not produce 7nm on time, resulting in AMD in CPU technology ahead, in order to return to the hegemony, Intel must compete for 3nm. It is precisely for this reason that Intel has become one of the competitors to TSMC's 3nm production capacity, competing with Apple.
Last year, it was reported that Intel squeezed out Apple to become the first customer of TSMC's 3nm process, mainly producing its next-generation processor and graphics products. At that time, the supply chain pointed out that Intel's products to TSMC included a graphics processor and three server processors, the first batch of about 4,000 pieces, is expected to be officially produced in May 2022, and produced in July.
According to industry reports, in order to compete for production capacity, in December last year, Intel CEO Kirsinger visited Taiwan on a private plane, hoping to win more TSMC advanced process production capacity in the next 2 to 3 years, covering processes including 7nm and optimized 6nm, 5nm and optimized 4nm, and 3nm. At that time, rumors pointed out that for the 3nm process, Intel proposed that it hoped that like Apple, TSMC could build a 3nm capacity special supply line for Intel.
A month later, in January 2022, it was reported that SMC planned to open a new production line for Intel's new production base in northern Taiwan, which is located in Baoshan District, Hsinchu City. The source said that Intel hopes that TSMC will use the 3nm manufacturing process to produce CPU and GPU parts for it.
From the above point of view, Intel is fighting a beautiful battle in the competition for 3nm production capacity.
apple
In the previously released chip roadmap, Apple expects to release a third-generation M series chip based on 3nm in 2023, and choose to be foundry by TSMC.
In 2020, the news about TSMC's 3nm production capacity is still all, "Apple is the first manufacturer to sign a 3nm process production capacity contract with TSMC", "all apple," TSMC 3nm first production capacity, iPhone all-inclusive" and so on, but the plan can never catch up with the change, and in the second half of 2021, Intel's "horizontal foot" makes Apple lose the qualification of TSMC's 3nm "exclusive favorite".
As A ten-year-old customer of TSMC and still the largest customer, Apple's 3nm production capacity should not be less than where to go, at present, for TSMC's 3nm production capacity, Apple has advanced a lot of money. But in terms of 4nm, Apple had to accept TSMC's price increase (but the increase will be lower than other advanced process customers) to ensure production capacity, and contracted 120,000-150,000 pieces of 4nm production capacity (the average price in 2022 is about 8-10% higher than in 2021), and at the 3nm stage, it may also be "historically reproduced".
Qualcomm
In December last year, there was news that Qualcomm intended to introduce Samsung's 3nm process, but from the recent news, the situation may change. According to Korean media reports, Qualcomm has allegedly handed over the order for 3nm AP processors to TSMC, which will be launched next year, and the reason for the order transfer is that Samsung's advanced process nodes are facing production problems.
Qualcomm is also a heavyweight customer of TSMC, and previously intended to hand over the 3nm order to Samsung because it could not compete for Apple's position in TSMC, in order to ensure sufficient production capacity to turn to Samsung, and now it is rumored that the order will be handed over to TSMC in the end because of the worry about Samsung's production problems.
AMD
According to the Taiwan media "Business Times" reported in May last year, AMD has booked 5nm and 3nm production capacity with TSMC in 2022 and the next two years, and is expected to launch a 5nm Zen 4 architecture processor in 2022 and a 3nm Zen 5 architecture processor from 2023 to 2024. However, like Qualcomm, AMD has also reported that it has tried to transfer Samsung because of capacity problems, which shows that insufficient 3nm production capacity may become the "original sin" of TSMC's loss of customers.
Judging from the current situation, with the rise of local GPU and DPU manufacturers, more and more companies will join the 3nm production capacity battle in the future, and the situation may be more lively than the current situation.
The "3nm Battle" of the foundry
At a time when chip design companies are still "fighting for production capacity", the field of wafer manufacturing is a different scene. For fabs, what is more important now is the breakthrough of 3nm. Whoever takes the lead in mass production of 3nm will occupy the commanding heights of the future wafer manufacturing industry, and even affect the product roadmap of chip giants such as AMD and Nvidia.
There is no doubt that at the 3nm node, only TSMC and Samsung can compete at present, but Intel is obviously also making efforts to advance the process. However, from the recent news, TSMC and Samsung two companies in the mass production of 3nm are quite bumpy. Gartner analyst Samuel Wang said the 3nm ramp will take longer than the previous node.
TSMC
Recently, a report citing sources in the semiconductor industry showed that TSMC reportedly had difficulties in terms of its 3nm process yield. The key rumor reported by the sources is that TSMC found it difficult to achieve satisfactory yields through its 3nm FinFET process. But so far, TSMC has not publicly acknowledged any N3 delays, instead claiming that it is "making good progress."
As we all know, TSMC 3nm adopts a fin field effect transistor (FinFET) structure in terms of transistors, and FinFET uses a three-dimensional structure to increase the contact area of the circuit gate, thereby making the circuit more stable, and also achieving the goal of continuous scaling of the semiconductor process. In fact, FinFET transistors walk in 3nm more or less is the limit, and then down will encounter the process of shrinkage and the current control leakage and other physical limit problems, and TSMC still choose a large part of the reason is that there is no need to change too many production tools, but also have a more advantageous cost structure. Especially for customers, it is a win-win situation to reduce production costs without too many design changes.
From the previous public data show that compared with the 5nm chip, the logic density of the TSMC 3nm chip will be increased by 75%, the efficiency will be increased by 15%, and the power consumption will be reduced by 30%. It is reported that TSMC's 3nm process has begun risky trial production in March 2021 and delivered in small quantities, and is expected to start commercial production in the second half of 2022.
Source: TSMC
From the perspective of the factory, the fourth to sixth phases of nanke 18 factory in Taiwan are TSMC's 3nm mass production base. In terms of customers, as can be seen from the above, Intel, Apple, Qualcomm, etc. have all chosen TSMC. Damo analyst Charlie Chan recently issued a report that TSMC is almost monopolistic in the 3nm chip foundry market in 2023, with a market share of nearly 100%.
Samsung
Unlike TSMC in terms of yield problems, Samsung's difficulty in 3nm is that the 3nm GAA process lags behind in the number of patented IP. According to South Korean media reports, Samsung's lack of patents related to the 3nm GAA process has upset Samsung.
Samsung uses a Gate-all-around (GAA) transistor architecture for transistors. Compared with TSMC's FinFET transistors, the cost of GAA-based 3nm technology is certainly higher, but from the performance point of view, GAA-based transistors can provide better electrostatic characteristics than FinFETs, meet certain Shanji width requirements, and can be expressed as the same process, using GAA architecture can make the chip size smaller.
Planar transistors, FinFETs and GAA FETs
Compared to the 5nm manufacturing process, Samsung's 3nm GAA technology has increased logic area efficiency by more than 35%, reduced power consumption by 50%, and improved performance by about 30%. Samsung officially announced in June last year that the 3nm process technology has successfully streamed the film. In addition, Samsung has also announced that it will launch an earlier version of the 3nm GAA in 2022, and its "performance version" will be shipped in 2023.
At present, in terms of factories, there is previous news that Samsung may invest $17 billion in the United States to build a 3nm chip production line. In terms of customers, Samsung has not disclosed specifically, but there have been news that Qualcomm, AMD and other TSMC heavyweight customers are interested in importing Samsung 3nm process, but between the above-mentioned Korean media reports that Qualcomm has handed over its 3nm AP processor foundry order to TSMC, Samsung 3nm customers are still a mystery.
After Pat Gelsinger became Intel's CEO last year, the IDM giant, which had tested the waters in the foundry space, is back in the market. At the same time, they also put forward very ambitious ambitions.
At the investor meeting on the 18th of this month, Intel CEO Pat Gelsinger once again stressed that the Intel 2nm process will be mass-produced in the first half of 2024, which is earlier than TSMC, which means that the competition between the wafer foundry business and TSMC will be more intense in 2 years.
Although Intel did not disclose too much in terms of the 3nm process, Digitimes' research report last year analyzed the transistor density problems of TSMC, Samsung, Intel and IBM on the same named semiconductor process nodes, and compared the transistor density of each company in 10nm, 7nm, 5nm, 3nm and 2nm.
The report shows that by the 3nm node, TSMC's transistor density is about 290 million /mm, Samsung has only 170 million /mm, and Intel will reach 520 million /mm. Intel's transistor density is more than 79% higher than TSMC's, reaching more than 2 times that of Samsung. Therefore, in terms of the transistor density index concerned by Moore's Law, in the same process node, Intel has certain advantages over the process technology of TSMC and Samsung's newer generation.
In terms of factories, Intel has stressed that it will spend 80 billion euros to set up factories in Europe, and Christin Eisenschmid, head of Intel Germany, revealed in an interview that it will produce 2nm or push smaller chips in Europe. Intel is making 2nm an important key to expanding its European production capacity to avoid falling behind in advanced technology competition in the future.
In general, at the 3nm node, TSMC, Samsung and Intel who will be the final winner may only be left to time to determine, but from the current situation, TSMC or slightly better.
Solution after 3 nm
3nm has reached the physical limit of Moore's Law, how to develop it in the future? This has become a solution that researchers around the world are desperately seeking. At present, researchers are mostly trying to find a way to crack in transistor technology and materials.
GAA transistors
The GAA transistors used by Samsung in the 3nm process are a good choice after 3nm, and the GAA design channel has gates around the four sides of the channel, which can reduce the leakage voltage and improve the control of the channel, which is the key when narrowing the process node. It is reported that TSMC will also use GAA transistors on the 2nm process.
Nanowires
Nanowires are nanostructures with a diameter of the nanometer range. One of the fundamental appeals of nanowire technologies is that they exhibit strong electrical properties, including high electron mobility due to their efficient one-dimensional structure.
Recently, researchers from HZDR announced that they have experimentally demonstrated long-standing theoretical predictions about nanowires under tension. In the experiment, the researchers fabricated nanowires consisting of a GaAs core and an aluminum shell of indium arsenide. Finally, the results show that the researchers can indeed improve the electron mobility of the nanowires by applying a tensile strain to the nanowires. The relative mobility increase measured to unsparatilized nanowires and bulk GaAs is approximately 30%. The researchers believe they could achieve a more significant increase in materials with greater lattice mismatches.
Stacked forked transistor technology
Recently, an Intel technology patent for "stacked forksheet transistors" has attracted attention.
Intel says the new transistor design could eventually enable a 3D and vertically stacked CMOS architecture that allows for an increase in the number of transistors compared to the most advanced tri-gate transistors currently available. In the patent, Intel describes the use of nanostrip transistors and germanium thin films, the latter of which will act as a dielectric wall, repeating in each vertically stacked transistor layer, ultimately depending on how many transistors are stacked on top of each other.
It is understood that Intel is not the first company to cite this manufacturing method, the Belgian research group Imec proposed this method in 2019, according to Imec's first standard unit simulation results, when applied to the 2nm technology node, compared to the traditional nanosheet method, the technology can significantly increase the transistor density.
Vertical transmission field effect transistor
Vertical transmission field effect transistors (VTFETs), jointly announced by IBM and Samsung, are designed to replace the FinFET technology currently used in some of today's most advanced chips. The new technology will stack transistors vertically, allowing current to flow up and down in a transistor stack, rather than placing transistors flat on a silicon surface as currently used on most chips and then flowing from one side to the other.
According to IBM and Samsung, this design has two advantages. First, it will allow many performance limitations to be bypassed, extending Moore's Law beyond the 1 nanometer threshold. At the same time, it can also affect the contact points between them to increase the current and save energy. They say the design could double performance or reduce energy consumption by 85 percent.
In fact, for how advanced processes evolve after 3nm, transistor manufacturing is only part of the solution, and chip design is also crucial, requiring on-chip interconnects, assembly, and packaging to minimize the impact on device and system performance.
Write at the end
Regarding the scramble for 3nm, the above is just the tip of the iceberg. In fact, around every link of the entire industry chain, there are almost a number of manufacturers competing on it. This is also the key to the development of integrated circuits so far.
In addition, although Moore's Law has reached its limit, whether it is a design company, a manufacturing plant or an encapsulation plant, they cannot stop the pace of advanced process research and development. To a smaller extent, advanced processes are related to the development of the industrial chain, and to a larger extent, advanced processes are related to national security. In the future, science and technology will be king in the world, and backwardness will be beaten, which is the iron law of gold rules.