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This chip will fully unlock the huge potential of DDR5 memory

This chip will fully unlock the huge potential of DDR5 memory

With the relevant products of major storage manufacturers successively listed, memory has officially entered the DDR5 era, and data centers will become an important scenario for DDR5 applications. "On the one hand, with the increasing amount of data, the increasing use of artificial intelligence and machine learning, and the continuous growth of edge computing, which will bring higher demand for memory and I/O bandwidth; on the other hand, the accelerated migration of data to the cloud, the increasing number of networked devices, and the increasing threat to data security." Su Lei, General Manager of Rambus Greater China, believes that the rapid growth of data centers is driving the demand for memory technology to continue to evolve.

The main advantage of DDR5 is that it offers more capacity and higher bandwidth. However, Chien-Hsin Lee, general manager of Rambus's interface chip division, pointed out that to keep up with the development of server technology, DDR5 also needs to meet four other requirements: one is to maintain the same memory read granularity (64 bytes of cache line); the other is to achieve the same or better reliability, availability and serviceability (RAS) function; the third is to maintain cooling power range (~15W/DIMM); and the fourth is to avoid excessive boot time.

Rambus recently introduced the second generation of DDR5 RCD (Registered Clock Driver) chips, which not only have data transfer rates of up to 5600MT/s, but also help DDR5 memory module (RDIMM) suppliers meet these challenges.

The chip has several highlights: reduced latency and power consumption while increasing the DDR5 data rate by 17%, and providing critical support for 5600MT/s DDR5 RDIMM for server main memory. Chien-Hsin Lee believes that the product shows Rambus's continuous leadership in the field of next-generation server memory interface chips, ensuring that RDIMM will not become a bottleneck restricting the development of technology during the development process.

He further pointed out that the DIMM memory interface chip reduces the number of loads, so that the overall capacity and performance are improved, but if no system or technical improvements are made, such an operation may bring about the corresponding bandwidth sacrifice, "Rambus through the related technology to solve this problem very well, so while increasing the memory capacity, the bandwidth has also been well improved." ”

By comparing DDR5 DIMMs with DDR4 DIMMs, we can see the overall improvement of performance, whether it is channel architecture, CA bus, burst length, DDR5 DIMMs are very obvious.

This chip will fully unlock the huge potential of DDR5 memory

Of particular importance is the significant increase in DRAM chip density. Chien-Hsin Lee said that DDR4 SDP can reach 16Gb, DDR5 is increased to 64Gb, resulting in a very important capacity increase in DIMMs, from 64GB in DDR4 to 256GB in DDR5. In addition, DDR4 enables the stacking of 8 DRAM, while with the latest stacking technology, DDR5 can realize the stacking of 16 DRAM. "Eventually the capacity of the DDR5 DIMM can even reach the terabyte level, which is a very big advantage."

Chien-Hsin Lee pointed out three designs for servers on the Rambus chip: one is the introduction of a new PMIC, which shifts power management from the motherboard to the DIMM itself to better adjust the power according to specific needs; the other is the introduction of I3C-HUB on the CA bus, which enables bandwidth to be increased by 10 times; and the use of thermal sensors, allowing the system to independently determine the output performance and power.

This chip will fully unlock the huge potential of DDR5 memory

Chien-Hsin Lee explains the changes to the power supply section design: "The first is to reduce the VDD voltage to meet the needs of the market, and after the migration of the PMIC from the motherboard to the DIMM, the noise and some other problems can be well controlled. ”

"After the design changes, including the reduction of the VDD, it did create some challenges for our overall design. In order to keep the performance the same or improve further, Rambus has always had a strong advantage in equalizer technology. In contrast to DDR4, it is very important that DDR5 introduces decision feedback equalization (DFE) technology. The use of DFE and second-generation RCD technology can help us solve these problems very well, reducing the voltage while maintaining relatively good performance. He stressed.

As domestic module manufacturers begin to ship DDR5 products one after another, the attention received by Rambus's RCD chips is increasing. "As a well-known IP vendor, Rambus has a 30-year history of implementing high-performance systems, Sulei said. It provides DDR5 memory interface chips with high performance and high design margin to meet the higher signal integrity and power integrity challenges faced by module manufacturers when designing and manufacturing DDR5. ”

This chip will fully unlock the huge potential of DDR5 memory

He concluded: "Rambus and China's partners have carried out close technical communication and cooperation around many hot spots in the data center, such as high-speed SerDes interface transmission, high-bandwidth and low-power HBM, and CXL data center interconnection. In terms of data center security, we have special security product solutions for static data and dynamic data security protection, which can escort data center security. Overall, we will be deeply rooted in the Chinese market, and adhere to the 'In China, for China' by continuously increasing investment and bringing the latest technology to Chinese partners. ”

(Proofreading/Andrew)

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