Source: Content by Semiconductor Industry Watch (ID: icbank) original, author: Chang Qiu, thank you.
The semiconductor process has progressed to 3nm, trial production will begin this year, mass production will be achieved next year, and then it will move to 2nm and 1nm. Relative to 2nm, the current 1nm process technology is completely in the stage of research and development exploration, there is no landing technology and capacity planning, and it is precisely because of this that 1nm technology has more imagination and expansion space, and the global industry, education and research are conducting research on related processes and materials.
Last week, IBM and Samsung unveiled a new design for vertically stacked transistors on a chip called Vertical Transport Field Effect Transistors (VTFETs). Current processors and SoCs, transistors sit flat on the surface of the silicon, and then current flows from one side to the other. In contrast, VTFETs are perpendicular to each other and current flows vertically. This technology is expected to break through the bottleneck of the 1nm process.
IBM and Samsung say the design has two advantages. First, it could bypass many performance limitations, extending Moore's Law beyond IBM's current nanosheet technology, and more importantly, the design reduces energy waste due to the larger current, which they estimate will make the processor twice as fast or 85% slower than chips designed with FinFET transistors. IBM and Samsung claim that this process technology is expected to allow the phone to be used for a full week on a single charge. They say it could also make certain energy-intensive tasks, including crypto mining, more energy efficient and therefore have less of an impact on the environment.
IBM and Samsung have not said when they plan to commercialize the process technology. They're not the only company trying to break through the 1 nm bottleneck. In May, TSMC and partners released the 1nm process technology path; in July, Intel said that its goal is to complete the design of the Essa-class chip by 2024. The company plans to use its new "Intel 20A" process nodes and RibbonFET transistors to achieve this.
TSMC remains a pioneer
In recent years, the scientific community has been looking for two-dimensional materials that can replace silicon, challenging the process process below 1nm, but has not been able to solve the problem of high resistance and low current of two-dimensional materials.
In recent years, TSMC has been an industry pioneer in the research and development and commercialization of advanced processes.
In May, TSMC, Taiwan University of Taiwan (NTU), and the Massachusetts Institute of Technology (MIT) jointly announced that a major breakthrough had been made in the development of 1nm chips.
This breakthrough is mainly reflected in the material aspect, the use of semi-metallic bismuth (Bi) as a two-dimensional (2D) material contact electrode, can greatly reduce the resistance and increase the current. This enables energy efficiency close to the physical limits of existing semiconductor sizes. The news came after IBM announced its 2nm chip earlier.
Each new process technology presents new challenges, in which case the key challenge is finding the right transistor structure and materials. At the same time, the transistor contacts that power the transistors are critical to their performance. Further miniaturization of semiconductor process technologies increases the contact resistance, thus limiting their performance. Therefore, chip manufacturers need to find a contact material with very low resistance, can transmit large currents, and can be used for mass production.
Using semi-metallic bismuth as the contact electrode for a transistor can greatly reduce the resistance and increase the current. Currently, TSMC uses tungsten interconnect transistors, while Intel uses cobalt interconnects. Both have their advantages and require specific equipment and tools.
To use semi-metallic bismuth as the contact electrode for the transistor, the researchers had to use a helium ion beam (HIB) lithography system and design a "simple deposition process." This process is only used for R&D production lines, so it is not fully prepared for mass production.
At present, TSMC's 1nm process node is still in the exploration stage, the factory is trying various options, and there is no guarantee that semi-metallic bismuth will be used in future mass production.
IMEC points to 2027
Recently, the Belgian Microelectronics Research Center (IMEC) said that the 1nm process can be commercialized in 2027, and the next 0.7nm is expected to achieve mass production after 2029.
Dr. Luc Van den hove, CEO of IMEC, stressed in an interview that with the new technology, "it is not a question of how many generations Moore's Law will advance." It is reported that the research and development of EUV equipment cooperated by IMEC and ASML is underway, and Japan's TEL is also involved, and it is expected that the test equipment will be completed in early 2023, and some companies intend to put into mass production in 2026.
In addition, IMEC has developed a new method to mitigate joule heating effects using metal interconnects in chips built using 1nm process technology.
IMEC researchers said that in experimental studies of aluminum-based binary compounds, the focus was on their resistivity, with the resistivity of stoichiometric AlCu and Al2Cu films as low as 9.5 Ωcm. These results experimentally support their commitment to use as new conductors in advanced semi-mosaic interconnect integration schemes where they can be combined with air gaps to improve performance. However, in this combination, the Joule heating effect becomes increasingly important. This is predicted by combining experimental and modeling efforts in a 12-tier back-end (BEOL) structure.
The 1nm process requires the introduction of new conductor materials, such as binary and ternary intermetallic compounds (e.g., Al or Ru bases), in the most critical layers of the rear end, with lower resistivity than conventional elemental metals (e.g., Cu, Co, Mo, or Ru) in a proportional size. IMEC has experimentally studied the resistivity of aluminide films, including AlNi, Al 3 Sc, AlCu and Al2 Cu. At thicknesses of 20 nm and above, all PVD deposited membranes have a resistivity comparable or lower than Ru or Mo. The minimum resistivity of the 28nm AlCu and Al2 membranes is 9.5 ΩcmCu – below the value of Cu.
IMEC envisions the introduction of intermetallic compounds into advanced semi-mosaic integrated schemes, including direct etching of patternable metals to achieve higher aspect ratio lines. RC latency can be further improved by gradually introducing some or all of the air gap between the metal wires. Replacing traditional low-k dielectrics with electrically isolated air gaps is expected to reduce the proportional size of the capacitance. However, the thermal conductivity of the air gap is extremely poor, which raises concerns about Joule heating under operating conditions.
IMEC quantified this challenge by performing Joule heating "calibration" measurements at the local 2-layer metal interconnect level and projecting the results into a 12-layer BEOL structure through modeling. The study predicts that the air gap will increase the temperature by 20%. The discovery of the density of the metal wire plays an important role: higher metal density displays help reduce Joule heating.
"These findings are key to improving the semi-mosaic metallization scheme as a 1nm process interconnect option," said Zsolt Tokei, IMEC researcher and director of the Nano Interconnect Program. "In addition, IMEC is expanding the interconnect roadmap with other options, including hybrid metallization and new intermediate-wire solutions, while addressing key challenges related to process integration and reliability."
How will it develop after 1nm?
When the silicon-based chip breaks through 1nm, the quantum tunneling effect increases greatly, which will form an "electron runaway" and make the chip ineffective. In this case, replacing the silicon substrate of the chip may be one of the feasible ways out for the further development of the chip.
Electrons can flow continuously from one gate to the next, rather than staying inside the expected logic gate, which essentially makes it impossible for a transistor to be closed.
Since the transistor consists of three terminals: the source, the drain and the gate. Current flows from the source to the drain and is controlled by a gate that turns the current on or off based on the applied voltage.
Both silicon and molybdenum disulfide (MoS2) have lattice structures, but the effective mass of electrons through silicon is smaller than that of molybdenum disulfide. When the gate length is 5 nm or longer, the silicon transistor can work properly.
While electrons passing through molybdenum disulfide have a higher effective mass, their flow can be controlled by a smaller gate length. The lawrence Berkeley National Laboratory has experimentally validated the feasibility of this protocol, but the study is still in a very early stage.
There are more than 1 billion transistors on a 14nm process chip, and the Berkeley Lab team has yet to develop a viable method to mass-produce new 1nm transistors, or even a chip that uses them.
But even as a proof of concept, the results here are still very important and encouraging, and it is expected that the discovery of subsequent new materials will continue to allow for smaller transistor sizes and consequently improve the energy efficiency of future chips.
China also has bright spots
At present, the global 1nm process is in the research and development exploration stage, and it is still a few years away from commercial production. Therefore, although the commercialization level of advanced process technology in Chinese mainland is not high, it is also following the international frontier in related theoretical research. For example, Hunan University also has a brilliant performance in the research of 1nm process technology.
In June, a research team at Hunan University developed a vertical field-effect transistor (VFET) with an ultra-short channel. This transistor technology can make the transistor 3nm in size, while the channel length only needs to be 0.65nm. In the previous process process, the length of the channel represents the chip process, that is to say, the length of the channel of 0.65nm means the 0.65nm process.
That is, the transistors are not arranged in parallel, but vertically. This longitudinal structure has a natural short channel characteristic, the semiconductor channel is located between the bottom electrode and the top electrode, and the channel length depends only on the material thickness.
What's more, this vertical field-effect transistor is not arranged in parallel, but vertically. This longitudinal structure has a natural short channel characteristic, the semiconductor channel is located between the bottom electrode and the top electrode, and the channel length depends only on the material thickness.
The researchers used van der Waals (vdW) metal electrode integration method to use molybdenum disulfide (MoS2) as a thin layer or even a single atomic layer of the semiconductor channel, that is, the length of the channel is actually the thickness of a layer of molybdenum disulfide material, so the shortest reaches 0.65 nm. Due to the different arrangements, there is no need to shorten the distance between the transistors and the transistors, and it is enough to build a brick-type layer by layer, which makes it not completely dependent on high-precision lithography machines. However, the research is only a product of the laboratory, and there is still a long way to go before it can really go to mass production.
Head to the 1nm lithography machine
The above is the process technology and material research and development, to achieve the landing of the 1nm process, manufacturing equipment, especially EUV lithography machine is essential, which has to mention ASML.
At present, ASML's main shipment EUV lithography machines are NXE: 3400B and 3400C, both of which have a numerical aperture (NA) of 0.33, of which the availability of the updated 3400C has reached about 90%.
ASML expects that by the end of this year, NXE:3600D will begin to be delivered, the matching set accuracy of the device will be improved, and the wafer throughput at 30mJ/cm2 will reach 160 pieces, an increase of 18% compared to 3400C, which will become the main equipment for TSMC and Samsung's 3nm process process in the future.
In addition, ASML also announced the future development plan of three generations of lithography machines, the three models are NEXT, EXE: 5000 and EXE: 5200. Starting with EXE:5000, the numerical aperture was increased to 0.55.
0.55NA has a huge improvement over 0.33NA, including higher contrast, lower image exposure costs, etc., which is the trend of future development.
At present, silicon wafers, exposure clean room has approached the physical limit, the current 5nm/7nm lithography machine has become very precise, equipment parts up to 100,000 +, volume of 40 containers. It is reported that the volume of 1nm lithography machine is twice as large as the current 3nm.
Since the lithography machine has a very large number of parts and requires high-precision assembly, the entire process of the lithography machine from shipment to configuration/training takes up to two years. According to this reference calculation, it is expected that the large-scale application of 0.55NA will be from 2025 to 2026, when the probability is that the trial production period of the 1nm process is expected.
epilogue
These are only representatives of the current R&D work related to the 1nm process in the industry, not all of them. It is believed that with the mass production of 3nm, and 2nm into the commercialization stage, the research and development of the 1nm process will gradually mature, and the current laboratory-level research is expected to have many of them landed in the fab, and at the same time, there will be newer processes and material technologies.