The GW1NSR family is based on GW1NS, integrates PSRAM/HyperRAM, facilitates caching, and includes GW1NSR-4C/4 devices. Among them, GW1NSR-4C represents a Cortex-M3, SoC chip, with the ARM Cortex-M3 hard processor as the core, with the minimum memory required to implement system functions; the embedded FPGA logic module unit is convenient and flexible, can achieve a variety of peripheral control functions, can provide excellent computing functions and abnormal system response interrupts, with high performance, low power consumption, small number of pins, flexible use, instantaneous start, low cost, non-volatile, high security, Rich package types and other characteristics. SoC devices realize the seamless connection of programmable logic devices and embedded processors, are compatible with a variety of peripheral device standards, can greatly reduce user costs, and can be widely used in industrial control, communications, Internet of Things, servo drives, consumption and other fields.
The FPGA hardware development environment is completely independent research and development, which can complete one-stop work such as FPGA synthesis, layout, routing, data streaming files and downloads.
1. Overview of characteristics
1.1 Low power consumption
- 55nm embedded flash memory process
- Core voltage: 1.2V
- GW1NSR-4C/4 supports LV version
- Support clock dynamic on/off
1.2 Integrated HyperRAM/PSRAM memory chip
1.3 Integrated NOR FLASH memory chip
1.4 Hard microprocessor
- Cortex-M3 32-bit ARM processor core
- ARM v7-M Thumb2 instruction set architecture optimized for small package embedded applications
- System timer that provides a simple 24-bit write-zero, decrement, self-loading counter with flexible control mechanism
- Thumb-compatible, Thumb-2 instruction set processors can get higher code density
- GW1NSR-4C supports operating frequencies up to 80MHz
- Hardware division and single-cycle multiplication
- Integrated NVIC to provide deterministic interrupt handling
- 26 interrupts with 8 priorities
- Memory protection unit, which provides privileged mode to protect the functionality of the operating system
- Unaligned data access, data can be loaded into memory more efficiently
- Bit-banding, precise bit operation, maximizes the use of storage space, improves the control of peripherals
- Timer0 and Timer1
- UART0 and UART1
- watchdog
- Debug ports: JTAG and TPIU
1.5 User Flash Resources
- GW1NSR-4C/4 embedded 256Kb storage
- 32-bit data bit width
1.6 Supports multiple I/O level standards
- LVCMOS33/25/18/15/12；LVTTL33，SSTL33/25/18 I，SSTL33/25/18 II，SSTL15；HSTL18 I，HSTL18 II，HSTL15 I；PCI，LVDS25，RSDS，LVDS25E，BLVDSE
- MLVDSE，LVPECLE，RSDSE
- Provides input signal de-hysteresis option
- Support 4mA, 8mA, 16mA, 24mA and other driving capabilities
- Provides output signal slew Rate option
- Output signal drive current option available
- Separate Bus Keeper, pull-up/pull-down resistors, and Open Drain output options are available for each I/O
- Supports hot swapping
- Support MIPI interface
- Support I3C
1.7 Rich basic logical units
- 4 input LUT (LUT4)
- Double edge trigger
- Supports shift registers
1.8 Supports multiple modes of static RAM
- Supports dual-port, single-port, and pseudo-dual-port modes
- Supports byte write enablement
1.9 Flexible PLL resources
- Realize clock multiplier, divide and phase shift
- Global clock network resources
1.10 Built-in Flash programming
- Instantaneous start-
- Supports safe bit operation
- Support AUTO BOOT and DUAL BOOT programming modes
1.11 Programming Configuration Mode
- Support JTAG configuration mode
- Supports FPGA on-chip DUAL BOOT configuration mode
- Supports multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL
2. Product information and package information list
GW1NSR-2/2C is not yet out
