Wen — Guo Ziwen
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Since 1946, the von Neumann architecture has laid the foundation for the separation of computer science software and hardware with the computer design concept of "stored programs". In the von Neumann architecture, computing and storage are at the heart of computer development. To this day, memory still plays a very important role in computers.
With the explosive growth of massive data and the increasing demand for computing power, memory is also evolving towards higher capacity, faster speed, lower energy consumption, and smaller size. In order to meet the increasingly complex and diverse market needs, the industry has always looked for a balance between DDR memory performance, capacity and power consumption. From DDR to DDR5, DDR memory standards and specifications have undergone "earth-shaking" changes, the operating voltage has gradually decreased, the chip capacity and data rate have been continuously improved, and the memory bandwidth has also been greatly improved.
DDR memory continues to evolve
Throughout the evolution of DDR memory, its iterative upgrade is closely related to the performance improvement of the processor. At the beginning of development, the computing power and data volume of the processor were not very large, and the memory existed directly in the form of DIP chips. Subsequently, the processor's demand for memory capacity continued to increase, and memory entered the SIMM era. During the iteration from 30Pin to 72Pin, the single memory bit width increased from 8 bits to 32 bits, and the memory capacity also increased from 256 KB to 512 KB or even larger.
With the continuous improvement of processor computing power and performance, higher requirements are also put forward for the capacity and performance of memory, and DIMM memory came into being. Dimm standard SDR SDRAM bandwidth is increased to 64 bits, which is in line with the processor bus width, significantly reducing system cost. Subsequently, Intel and Rambus jointly launched Rambus DRAM, but due to high cost, high frequency, low efficiency and other issues have not yet been fully popularized.
The final success of entering the market was DDR SDRAM, which is double data rate synchronous dynamic random access memory. Compared with SDR SDRAM, DDR SDRAM will trigger signal transmission during the clock cycle, encountering both rising and falling edges, and the power consumption has not increased, but the data transmission rate has doubled. At the same time, in order to balance memory controller compatibility and performance, the addressing and control signals are transmitted only on the rising edge.
For the latest DDR5 standard, DDR5 has significantly improved performance, capacity, and power consumption compared to DDR4. It can be intuitively seen that the DDR4 data transmission rate can reach a maximum of 3.2Gbps, and under the new DDR5 standard, for the first time, 4.8Gbps is the benchmark, and the highest data transmission rate can reach 8.4Gbps, which is more than 50% higher than the DDR4 data rate. From the perspective of memory voltage, the memory voltage of DDR5 is also reduced from 1.2V to 1.1V in DDR4, and the signal source is updated to a PODL signal.
DDR5 performance index (Source: JEDEC)
In terms of channel architecture, DDR5 has two channels per DIMM, and each DIMM provides two independent 40-bit data channels (including 8-bit ECC), and the cache line is still 64 bytes. Although the number of memory pins has not changed, it is still 288, but the individual pins are defined differently and are not backward compatible. As a result, memory latency is reduced and memory efficiency is greatly improved. In addition, the DDR5 SDP was increased to 64GB and the DIMMs capacity was increased to 256GB. With the new stacking technology, the DDR5 enables 16 DRAM stacks.
DDR5 memory structure (Source: Rambus)
Step into the era of DDR5 memory
After the JEDEC Solid State Technology Association announced the release plan of the DDR5 memory standard in 2017, many leading players such as Samsung, Micron, and SK Hynix began to bet on DDR5 memory in an attempt to compete for market discourse at an iterative speed. However, it wasn't until July 2020 that the DDR5 memory standard was officially released, which was a full two years later than JEDEC expected, but the memory frequency started at 4800MHz, which was much higher than expected.
For the DDR5 memory standard, the JEDEC Solid State Technology Association considers it a revolutionary memory architecture. With the rapid development of data centers, edge computing, etc., especially after the full launch of the "East, West, And West" project, the demand for low latency, low power consumption, large bandwidth and high rate has further increased. According to Yole's forecast, starting in 2022, the DDR5 memory market will cut from the server market and continue to expand to mainstream markets such as mobile phones, laptops and PCs. It is expected that by 2023, DDR5 will be widely used in these areas, shipments will continue to increase, and the application transition from DDR4 to DDR5 will be gradually completed.
Under the trend of chip suppliers and module manufacturers increasing the layout of DDR5 memory, Intel, AMD and other manufacturers have also successively launched products and platforms that support DDR5 memory. Some time ago, Tom's Hardware news pointed out that Samsung and SK Hynix already have plans to stop the production of DDR3 memory. This also means that DDR3 memory is about to withdraw, and DDR5 memory will enter the golden development period of volume growth, and the ecosystem will be further improved.
The true popularity of DDR5 memory will take two to three years, and according to market research agency Omdia, the market share of DDR5 memory will reach 10% in the entire DRAM market in 2022, and further increase to 43% in 2024.