2D materials can further reduce the size of transistors and are a feasible solution for extending Moore's Law.
Back in 1965, computer scientist Gordon Gordon Moore first hypothesized that the number of transistors that can fit on an integrated circuit doubles every 18 months, while doubling the speed and storage capacity of computers. This is moore's law famous in the field of semiconductors. Now, a fingernail-sized chip can carry tens of billions of transistors, while the number of transistors that can be crammed into a single chip is almost at its limit.
To keep Moore's Law going, you might think of shrinking transistors to only atomic thickness. Unfortunately, this idea doesn't apply to silicon. Because the semiconductor properties of silicon require a third dimension. But there is a class of materials that can act as semiconductors, even though they are two-dimensional. Recent results from some chip companies and research institutes suggest that these 2D semiconductors may be a good choice once silicon reaches its limits.
At the 2021 IEEE International Electronic Device Conference (IEDM 2021) in San Francisco, researchers from Intel, Stanford, and TSMC proposed a separate solution to one of the toughest hurdles in manufacturing 2D transistors: sharp resistance spikes where semiconductors come into contact with metals. Meanwhile, engineers from IMEC, the Inter-University Center for Microelectronics, showed how they cleared the way for commercial-grade transistor manufacturing processes and showed how smallest 2D transistors would go in the future. In addition, researchers from Beijing and Wuhan have constructed 2D equivalents of silicon devices.
Intel, Stanford, and TSMC are exploring 2D semiconductors, among others
Krishna Saraswat, a professor of electrical engineering at Stanford University, said: "Silicon has reached its limits, and people claim that Moore's Law is over, but in my opinion this is not the case. Moore's Law can continue into the third dimension. For this, we need 2D semiconductors or something like that. Professor Saraswat is joined by fellow Professor Eric Pop and H.-S. from Stanford University. Professor Philip Wong works on 3D chips together.
2D semiconductors belong to a class of materials called transition metal dichalcogenides. Among them, the most widely studied is molybdenum disulfide (MoS_2). Theoretically, electrons should pass through tungsten disulfide (another 2D material) faster than molybdenum disulfide. But in Intel's experiments, molybdenum disulfide devices are superior.
In previous studies, gold was the preferred contact for forming transistors with molybdenum disulfide, but depositing gold and other high melting point metals can damage molybdenum disulfide. So Krishna Saraswat Professor student Aravindh Kumar experimented with indium and tin with a melting point below hundreds of degrees Celsius.
But indium and tin melting point values are so low that these metals melt during late processing and packaging of the chip, when the chip is exposed to temperatures of up to 300-500 degrees Celsius. To make matters worse, these metals are oxidized during processing. Kumar solves this by fusing low melting point metals with gold to form an alloy. First Kumar deposits indium or tin on molybdenum disulfide to protect the semiconductor, and then covers it with gold to isolate oxygen. The process produces a Sikkim alloy with a 270 ohm-micron resistance and an indium gold alloy with a 190 ohm-micron resistance, and both alloys remain stable at at least 450 degrees Celsius.
Deposited gold destroys 2D semiconductors. But indium and tin are deposited on molybdenum disulfide, protecting the semiconductor
Unlike kumar's research, chipmakers TSMC and Intel found different solutions — antimony. Han Wang, of TSMC's specialty on low-dimensional chips, said that by using semi-metals as contact materials, the energy barrier between semiconductors and contacts is reduced. Semi-metals, such as antimony, are materials with zero band gap between metals and semiconductors, resulting in a very low Schottky barrier, resulting in low resistance on both TSMC and Intel devices.
Previously, TSMC had studied another semi-metal, bismuth, but its melting point was too low. Wang says antimony has better thermal stability, which means it's more compatible with existing chip manufacturing processes, resulting in more durable devices and allowing for greater flexibility in the second half of the chip manufacturing process.
In addition to making better devices, IMEC researchers are exploring ways to integrate 2D semiconductors on commercial 300mm silicon wafers. Using 300mm wafers, IMEC explored how small a 2D device can eventually reach. The researchers used tungsten disulfide as a semiconductor, which in turn formed a double gate transistor, in which tungsten disulfide is sandwiched between the top and bottom electrodes to control the passage of current. By using pattern tricks, they reduced the top gate to less than 5 nanometers. But the performance of this particular device is not ideal, but the researchers point to ways to improve it.
IMEC fabricated a tungsten disulfide transistor with a gate length of less than 5 nanometers
Today, mainstream chip architectures use transverse transmission field-effect transistors (FETs), such as fin-type field-effect transistors (FinFETs), so named because the silicon body resembles a fish dorsal fin. FinFETs are designed to layer transistors along the wafer surface, with current flowing horizontally. But to continue to shrink the size of devices while still driving enough current through, leading chipmakers are turning to nanoscale devices.
While dual-gate devices like IMEC are the standard for 2D research, engineers from Peking University and the National Center for Pulsed Strong Magnetic Field Science go a step further. The research team led by Professor Wu Yanqing simulated this structure using two layers of molybdenum disulfide. It turns out that the device is more than just the sum of its parts, and the transconductance of the 2D nanosheet is twice as advanced compared to its single-layer device, which means that for a given voltage, it can drive more than twice as much current as other devices.
Intel simulated a more extreme version of the stacked 2D device, where the researchers used six layers of molybdenum disulfide and a 5-nanometer gate length, while Professor Wu Yanqing led the research team to use only two layers of molybdenum disulfide and a 100-nanometer gate length. Compared to analog silicon devices with the same vertical height and 15 nm gate length, the 2D devices are packaged in two nanosheets for better performance. Although electrons pass through molybdenum disulfide more slowly than through silicon, and the contact resistance is much higher.
A CMOS chip consists of pairs of N-MOS and P-MOS devices. To cram more devices into silicon wafers, chipmakers want to stack the two types of devices on top of each other rather than side-by-side. At last year's IEDM, Intel demonstrated such a silicon device called Complementary FETs (CFET).
NMOS and PMOS devices are typically placed side-by-side on the chip. Intel found a way to stack them together to compress the circuit size. Image source: Intel
The research team led by Professor Wu Yanqing also tried the same method, replacing the molybdenum disulfide layer in the stacked device with tungsten diselenide. Then, by modifying the connection between the source and drain, the 2D CFET becomes an inverter circuit that occupies essentially the same footprint as a single transistor.
Obviously, there is still a lot of work to be done before 2D semiconductors can be manufactured on a large scale, but with advances in contact resistors and the success of new experiments, we can expect developments in this area.