At the 2021 IEEE International Electronic Devices Conference (IEDM) in San Francisco, Intel announced key technological breakthroughs in packaging, transistors, and quantum physics, as well as advances in advanced processes. In the eyes of the outside world, Intel announced a number of breakthroughs in a high-profile manner, intending to publicly compete with TSMC and Samsung.
In July, Intel released the most complete technology roadmap in history, adding semiconductor process processes and packaging technologies, hoping to return to industry leadership with innovative research. Intel has published a number of papers in IEDM2021 to show its muscles to the outside world, saying that this is the most technological breakthrough in Intel's history.
A few days ago, Lu Donghui, vice president of Intel Manufacturing, Supply Chain and Operation Group and co-general manager of the strategic planning department, explained in detail a number of technological breakthroughs to the media. He said at the meeting that the most difficult thing in research is to explore the road, just like a climber can see where the top of the mountain is at a glance, but it is not clear how to go and how much supplies to bring.
In view of the problem of how to integrate more transistors in future products, Intel is focusing on core microfilm technology, and there are three main research breakthroughs.
The breakthrough one is to use hybrid bonding technology to increase the interconnect density in the package by more than 10 times, corresponding to the Plan for The Coveros Direct (3D packaging technology) that Intel announced in July this year. In the context of the industry's competition for advanced processes, 3D stacking technology has become the focus of research by major manufacturers, and Intel's packaging technology breakthrough announced this time shows its strength in 3D stacking technology.
Lu Donghui explained that the traditional technology is to connect the two chips through solder, and the hybrid bonding technology that Intel is studying is to let the metal pads touch directly, which will produce molecular bonding. "Its biggest benefit is that the density of the connection will increase dramatically, at least 10 times." This would allow for up to 10,000 connections per square millimeter, which is very tight. There will be billions of transistors on the chip in the future, or tens of billions of transistors, and finally they will be connected, so this is a very critical breakthrough. Lu Donghui said.
Lu Donghui pointed out that the process of this technology is very sensitive and requires mechanical polishing to smooth the surface, so the optimization of chemical mechanical polishing (SNP) and deposition is very critical. In addition, industry-uniform standards and test procedures are also required.
The breakthrough two is to achieve an increase of 30% to 50% of the shrinkage area of transistors, corresponding to Intel's previously announced GAA RibbonFET technology, which will be used on Intel 20A and launched in 2024 in the form of a 2nm process. Both TSMC and Samsung plan to put in mass production of 2nm processes in 2025, and Intel's high-profile announcement of a breakthrough in advanced processes is a public battle with TSMC and Samsung.
Intel announced in the paper a new breakthrough in the technology on 3D CMOS stacking, with two approaches. Method one is sequential, the specific process flow is to do a good job of the lower layer of wafers first, and then turn the upper layer over and then make another layer of wafers, which can effectively improve performance; method two is self-alignment, one is through the lithography machine alignment, the other is called self-alignment, to make the wafer automatically aligned by dry erosion or deposition means. Intel's self-alignment achieves a gate spacing of 55 nanometers, which Lu Donghui said is "a very remarkable breakthrough."
Breakthrough three is the discovery of new materials on the way to enter the Amy era for Moore's Law. Intel proposed replacing silicon with a two-dimensional material called TMD (transition metal sulfide) to become a current channel, characterized by a very thin, single-layer atomic layer of disulfide underneath the channel, which can be used as a shorter channel. "The problem with silicon is that it can't continue to shrink down, and there will be a lot of quantum effects when it shrinks down, but two-dimensional materials have their own characteristics, so they can be done very small." Lu Donghui pointed out that Intel's biggest breakthrough in materials is to use two different metals to do metal contact, NMOS uses antimony, PMOS uses ruthenium, which can make the capacitor smaller.
In addition, in terms of power devices, Intel announced two breakthroughs, one is the first time to integrate gallium nitride (GaN-based) power devices with silicon-based CMOS on 300 mm wafers. The second is to achieve a read/write capability of 2 nanoseconds in ferroelectric memory.
In the field of quantum computing, Intel demonstrated the world's first room temperature magnetoelectric spin orbital (MESO) logic device, which indicates that it is possible to manufacture new transistors based on nanoscale magnet devices in the future. It is reported that Intel and the Belgian Microelectronics Research Center (IMEC) have made progress in the research of spin electronic materials, making the device integration research close to the full practical application of spintronic devices.