In the daily work of the chip front-end design engineer, it is necessary to use the hardware description language Verilog HDL to implement various algorithms/protocols, etc., and then perform RTL function simulation in order to verify whether the behavior of the circuit is consistent with the assumption in the software environment. This also means that engineers spend a lot of time using digital emulators to verify the chip before tape-out and ensure that it functions correctly.
As an indispensable part of chip verification, simulation technology is the key sign-off technology to ensure the normal function of the chip, through the computer combined with test incentives to simulate the operation of the chip in the real environment, to help engineers through a variety of debugging means to determine whether the running results are in line with expectations. The digital simulator is mainly for the simulation of digital circuits, the design engineer needs to apply the hardware description language to design the circuit, and the verification engineer also needs to use the abstraction layer HDL to build the test environment; the simulation tool needs to interpret and compile these HDL codes, and calculate the simulation results so that the engineers can check the results.
As design verification languages and methodologies continue to evolve, a variety of application platforms are emerging. This series of technological developments has brought unprecedented challenges to digital simulators. Designing competitive systems-on-chip (SoCs) requires the rational use of a variety of sophisticated technologies. For digital emulators, the challenge is not only the growth of chip scale, but also a series of problems that come with it, including: limited computing power, low debugging efficiency, and single platform.
For many years, the industry generally believes that a good digital emulator should have the following conditions:
- Ensure the correctness and consistency of simulation results, and meet the requirements of sign-off (sign-off).
- Support for IEEE1364 and IEEE1800 standard syntax, with compliance with syntax points and function points
- Emulator core can achieve efficient scheduler, flexible and powerful random solver
-In terms of debugging, the tool should closely integrate various debugging applications to improve the effectiveness of debugging
But further, in view of the pain points of the current situation of industrial development, advanced digital simulators should also have the following characteristics:
-In order to further take advantage of the new computing architecture and platform, in addition to the traditional X86, it can seamlessly support other new processor architectures such as ARM and native cloud computing architectures, and can effectively use parallel computing to support high-performance compilation and computing
- Emulators and other verification tools have a high degree of integration, and a unified coverage data structure to ensure the effectiveness of coverage collection of various tools
The core R&D team of The Core Huazhang Simulator has decades of R&D experience in related fields, has successfully led large-scale simulator projects in multinational companies, and has rich technical reserves for verification language, methodology, simulator core architecture, algorithm and optimization.
Based on the judgment of the development trend of cutting-edge technology, and combined with the challenges of the industry reality for in-depth research and exploration, after more than a year of research and development accumulation, and after being polished by a number of well-known customers in China, Xinhuazhang launched an independent and new architecture of the domestic leading level simulator - Dome GalaxSim. The product innovatively uses a new software framework, provides multi-platform support, and has been tested on multiple arm-based domestic architectures.
At present, Dome GalaxySim supports IEEE1800 SystemVerilog syntax, IEEE1364 Verilog syntax, and IEEE1800.2 UVM methodology, which has reached the level of mainstream commercial simulators in semantic parsing, simulation behavior, and timing model. Dome GalaxySim emulator can provide a unified coverage database, and is compatible with other verification tools such as The Dome GalaxyFV under The Core, combined with the rich test scenarios provided by the Dome GalaxyPSS intelligent verification system, can accelerate coverage convergence, efficiently solve the problem of lack of compatibility of other tools in the industry, and further improve the verification efficiency.
Use a validation instance of vault GalaxySim
In order to verify the functional correctness of the GalaxySim simulation, the ease of debugging, and whether the performance can meet the needs of customers, we specially run the Hummingbird E203 open source RISC-V CPU design based on the Verilog language on the emulator of The Core Huazhang as a demo demo.
Hummingbird E203 is the first open source RISC-V processor in China, which has accumulated a wide range of users since its release in 2018. The E203 core adopts a 2-stage pipeline structure, can run RISC-V instruction sets, supports the configuration combination of instruction subsets such as RV32IMAC, and has industrial-grade development standards, which is in line with the new trend of current processor architecture development towards DSA (Domain Specific Architecture), so it has a wide range of representatives.
Open source Hummingbird E203 SoC overall block diagram
The Dome Emulator first needs to read the chip design, then parse and abstract it, convert it into a compact and efficient data structure inside the emulator, and quickly generate a native platform emulator based on a new generation of compilation technology. At the same time, we open the waveform debugging tool, and the IC engineer can run the simulation program to verify it.
After the compilation is complete, we execute the emulator. After the program is run, a file dump of the signal waveform is also made for debugging. The environmental technology in this verification example includes a variety of localization products, involving chip design, processors, servers, operating systems and other links.
Dome GalaxSim is based on the Core Huazhang FusionVerify Intelligent V verification platform, which supports the new waveform format and waveform debugging tools independently developed, allowing users to easily view the signal waveform, quickly locate the defective time slice and abnormal signal, and repair it.
At the same time, we run the same design on a third-party emulator. In this way, on the one hand, the simulation results are compared to explore the correctness of the function, and on the other hand, the efficiency of the simulation can be compared, which is convenient for comparing the performance indicators of the tool.
After actual measurement and comparison, the GalaxSim running results are completely consistent with the commercial simulator, and the performance is also up to the expected requirements. After several customers tried hummingbird demos running on The GalaxySim, they expressed high recognition of the product: smooth debugging tools, user interface friendly operation, and support for different processor architectures.
Product Highlights
The first simulator proposed in China to support multiple architectures, with:
- Flexible portability, friendly software and hardware ecological support
- Support different processor computing architectures, including X86, ARM, MIPS, RISC-V, NPU, GPGPU, etc
Most of the traditional EDA tools are highly coupled to a single CPU architecture, for example, some EDA tools only support the X86 platform. Once you need to migrate to another platform, the R&D effort required is enormous. Nowadays, the processor ecology is becoming more and more diverse, the future platform is no longer a single processor platform, reducing the coupling of EDA tools to the underlying CPU architecture, allowing users to deploy tools on any platform more effectively, and also allowing products to have more application space.
Full support for a variety of HDL syntax, semantic parsing consistency is strong
- Compatible with the Verilog standard IEEE1364
- Full support for SystemVerilog, UVM standards (IEEE1800, IEEE1800.2)
- Native support, no need to modify the customer source code
The correct syntax parsing of the emulator determines whether it can correctly understand the design intent, and also avoids the same code producing different simulation results under different emulators. The semantics of these two languages, as defined by the Verilog standard (IEEE1364) and the System Verilog standard (IEEE1800), are very complex, with many keywords and nearly infinite combinations. Dome GalaxySim can consider all aspects of the syntax and various boundary scenarios when building test cases for the emulator, so as to achieve comprehensive and complete testing.
Excellent commissioning capabilities and rich observability
- Support VCD and FSBD waveform export (with third-party libraries)
-Support XEDB, a self-developed waveform format of Xinhuazhang
- Supports fast code coverage
The focus of commissioning is on observability and controllability. Dome GalaxySim provides a variety of effective data representations for different scenarios, and can synchronize data annotation (annotation) between different data forms. In addition, dome GalaxySim lowers the barrier to entry for tool use, allows novice users to master debugging techniques very quickly, and provides an interface for secondary development of the common language.
The excellent performance of the Dome GalaxySim is highly recognized by the ecological partners.
Chen Gang, Associate Researcher, Institute of Semiconductors, Chinese Academy of Sciences
Using the GalaxySim simulation tool, we tuned the design in two weeks. The comparison results with other commercial simulators show that the Core Chinese GalaxySim has correct behavior for RTL behavior simulation, and in terms of performance, many scenarios and other commercial tools have been basically consistent. We look forward to further cooperation with Xin Huazhang."
Huang Wuxin Huazhang Technology Product and Business Planning Director
In order to ensure the compliance of the syntax and the accuracy of the simulation, we have carried out a variety of rigorous tests on the product, including the analysis of IEEE1364 and IEEE1800 syntax points, and the comparative test combined with the mainstream commercial simulator to ensure that the tool is consistent in semantic parsing, simulation behavior, and timing model, thus effectively helping users improve verification efficiency and accelerate verification convergence.