Wen — Guo Ziwen
Figure - Tereda
From the design to the manufacture of the chip, and then to the packaging and testing, the process of turning sand into gold consumes a lot of manpower, material and financial resources, and the quality, performance and yield of each link need to be strictly controlled. As we all know, simple chip testing cannot add functions to the chip, nor can it improve the performance of the chip. However, chip testing runs through the entire process from semiconductor research and development to mass production, becoming a link that cannot be bypassed in semiconductor manufacturing. Chip testing mainly includes wafer test CP and finished product test FT, through testing, manufacturers can find chip design and manufacturing problems in time, thereby improving chip production yield and ensuring shipment quality.
In the semiconductor test equipment market, ATE test equipment accounts for two-thirds of semiconductor test equipment. Among them, TERADYNE and EdWin testing have the strongest technical strength, controlling 90% of the global semiconductor test equipment market share. Tereda has a strong accumulation of technology, has a complete semiconductor test solution, continues to ensure chip quality, and reduces customer test costs. According to Huang Feihong, deputy general manager of sales of Teradyne, for SoC testing, Teradyne has launched a variety of test platforms, including J750, UltraFLEX, EAGLE TEST SYSTEM and other series of test equipment.
In Huang Feihong's view, to a certain extent, the test time is equivalent to the test cost. Therefore, how to improve the efficiency of chip testing and reduce the cost of testing has become an urgent problem to be solved in the current semiconductor market. Based on ultraFLEX test equipment, Teradyne introduced UltraFLEXplus, which uses a new PACE architecture combined with IG-XL software to add another tool to the semiconductor test market.
The chip process continues to plummet, and the test challenges are becoming increasingly prominent
Judging from the evolution of the semiconductor process process, it can be roughly divided into three eras. It can be seen that from 1990 to 2025, the semiconductor process gradually descended from 0.8um to 3nm or even 2nm, and as the semiconductor process continued to evolve, the chip size became smaller and smaller, and the on-chip transistor integration became higher and higher. This means that more analog, data transmission and interface functions are integrated on the chip. Correspondingly, chip test technology has evolved to meet the increasingly complex demands of chip functions.
"The evolution of advanced processes has led to an increase in test time." Huang Feihong pointed out that the increasingly large chip scale continues to increase the complexity of chip design, and the demand for TESTSCAN, BIST, standardized interfaces and so on has also increased. Taking the processor chip as an example, SCAN and BIST testing are the standards for verifying the maturity of the process, and the smaller the process size, the longer the test time. For analog and RF chips, Trimming testing is taking up more and more time.
In addition, single-station testing seriously slows down the chip test speed and lengthens the test time, resulting in a high proportion of test costs in the overall chip price. The further advanced technology is explored, the higher the requirements for the parallel testing capabilities of test equipment. And the process down to 10nm below, the number of transistors has grown far more than the update speed of chip test technology, interface boards and test stations can not be increased indefinitely, ATE test equipment is facing a new round of challenges.
"Another challenge [for ATE test equipment] is that as the process size is reduced to 10nm and below, the yield of the first series production of wafers continues to decline." Huang Feihong said that the die size of a single chip has increased from the original 200mm2 to 800mm2, and the corresponding failure density is also increasing. For the 800mm2 die size, the yield of the wafer's initial mass production is less than 10% under the 10nm process.
The underlying architecture has been upgraded to reduce costs and increase efficiency for chip testing
In the face of more complex mobile phones, processors, RF and other chips, Teradyne launched the UltraFLEXplus high-performance SoC test platform. On the basis of the UltraFLEX series of test platforms, the platform has a completely new design of the detector interface board and, for the first time, adopts the PACE multi-controller architecture. "From the J750 to UltraFLEX to UltraFLEXplus, Teradyne has adopted a unified software platform, IG-XL." In Huang Feihong's view, this is also the biggest competitive advantage of Teradyne, the test program can be fully compatible, directly improving the development efficiency of engineers.
Different from the previous generation interface board design, UltraFLEXplus adopts the new Broadside technology, and the interface board size is increased, and the number of PCB layers will be greatly reduced by 20%. "If there are many PCB layers, the processing difficulty will lead to greater failure rates." On the other hand, the pins of the new interface board are symmetrically distributed, the layout and wiring are clearer, the winding length is effectively reduced, the PCB board design requirements can be effectively reduced, the signal integrity and power integrity are greatly improved, and the parallel testing ability is also improved.
"The PACE multi-controller architecture is unique to the UltraFLEXplus test platform, which can decentralize computing power and improve processing efficiency." Huang Feihong said that the PACE architecture through the intermediate workstation master control, the entire computing power is delegated to each board, and each board's independent CPU performs instructions and measurement calculations. In addition, UltraFLEXplus is equipped with the third generation of digital boards, using open, scalable, distributed computing and other architectures, which can improve the overall test efficiency, combined with the IG-XL software platform, reduce the engineering development time by 20%, and develop more optimized test procedures in less time.
Write at the end
According to Huang Feihong, the global installed capacity of the UltraFLEX test platform has reached 5,000 sets, and the installed capacity of the IG-XL software platform has exceeded 12,000 sets. Since 2020, UltraFLEXplus has also been installed in close to 600 units worldwide, and has been installed in two major foundries and five OSAT. Tereda has rich experience in market verification, and within a year and a half of the release of the new UltraFLEXplus platform, it has been widely praised by major customers and applied in the field of digital computing chips.