The GW1NS family includes GW1NS-4C devices and GW1NS-4 devices with embedded ARM Cortex-M3 hard processors and user flash memory. The GW1NS-4C device features the ARM Cortex-M3 hard processor as the core, with the minimum memory required to implement system functionality, and the embedded FPGA logic module unit is convenient and flexible, enabling a variety of peripheral control functions, providing excellent computing functions and abnormal system response interrupts. The GW1NS-4C device realizes the seamless connection of programmable logic devices and embedded processors, is compatible with a variety of peripheral device standards, can greatly reduce user costs, and can be widely used in industrial control, communications, Internet of Things, servo drives, consumption and other fields.
There are designs similar to microcontrollers or microcontrollers + FPGAs that can be replaced by this high-cloud chip. In addition, the FPGA hardware development environment is completely independent research and development, which can complete one-stop work such as FPGA synthesis, layout, cabling, data stream file generation and download. M3 software development can use KEIL or Gaoyun's self-developed GMD, which is convenient for inheritance.
1. Characteristic description
1.1 Low power consumption
- 55nm embedded flash memory process
- Core voltage: 1.2V
- GW1NS-4C/4 supports LV version
- Support clock dynamic on/off
1.2 Hard microprocessor
- Cortex-M3 32-bit RISC kernel
- ARM3v7M architecture, optimized for small package embedded applications
- System timer that provides a simple 24-bit write-zero, decrement, self-loading counter with flexible control mechanism
- Thumb-compatible, Thumb-2 instruction set processors can get higher code density
- GW1NS-4C supports operating frequencies up to 80MHz
- Hardware division and single-cycle multiplication
- Integrated NVIC to provide deterministic interrupt handling
- 26 interrupts with 8 priorities
- Memory protection unit, which provides privileged mode to protect the functionality of the operating system
- Unaligned data access, data can be loaded into memory more efficiently
- Bit-banding, precise bit operation, maximizes the use of storage space, improves the control of peripherals
- Timer0 and Timer1
- UART0 and UART1
- watchdog
- Debug ports: JTAG and TPIU
- Plug and play
- Hot-swappable
1.3 User Flash Resources
- GW1NS-4C/4 embedded 32K Byte storage space
- 32-bit data bit width
1.4 Supports multiple I/O level standards
- LVCMOS33/25/18/15/12；LVTTL33，SSTL33/25/18 I， SSTL33/25/18 II，SSTL15；HSTL18 I，HSTL18 II，HSTL15 I；PCI，LVDS25，RSDS，LVDS25E，BLVDSE
- MLVDSE，LVPECLE，RSDSE
- Provides input signal de-hysteresis option
- Support 4mA, 8mA, 16mA, 24mA and other driving capabilities
- Provides output signal slew Rate option
- Output signal drive current option available
- Separate Bus Keeper, pull-up/pull-down resistors, and Open Drain output options are available for each I/O
- Supports hot swapping
- GW1NS-4C/4 BANK0/BANK1 supports MIPI I/O input, MIPI transmission rate up to 1.2Gbps
- GW1NS-4C/4 BANK2 supports MIPI I/O output at MIPI transmission rates up to 1.2Gbps
- GW1NS-4C/4 BANK0/BANK1/BANK2 supports I3C
1.5 Rich basic logical units
- 4 input LUT (LUT4)
- Double edge trigger
- Supports shift registers
1.6 Supports multiple modes of static RAM
- Supports dual-port, single-port, and pseudo-dual-port modes
- Supports byte write enablement
1.7 Flexible PLL Resources
- Realize clock multiplier, divide and phase shift
- Global clock network resources
1.8 Built-in Flash programming
- Instantaneous start-
- Supports safe bit operation
- Support AUTO BOOT and DUAL BOOT programming modes
1.9 Programming Configuration Mode
- Support JTAG configuration mode
- Supports FPGA on-chip DUAL BOOT configuration mode
- Supports multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL
2. Product information and package information list
Table 2-1 Product information list
GW1NS-2/2C is not yet out
Table 2-2 Product Package and Maximum User I/O Information, LVDS Log
