GW1NR is a memory chip with rich capacity integrated on the basis of GW1N, and the memory type and capacity of different package types are different, as detailed below. The advantage of sealing is that some applications can save memory chips, but also save PCB area, such as the original design of SDRAM + FPGA, now only a high cloud FPGA is required. It also has the characteristics of low power consumption, instantaneous start, low cost, non-volatile, high security, rich package types, and convenient and flexible use. In addition, the FPGA hardware development environment is completely independent research and development, which can complete one-stop work such as FPGA synthesis, layout, cabling, data stream file generation and download.
1. Characteristic description
1.1 User Flash Resources (GW1NR-1)
- 100,000 write life cycles
- More than 10 years of data retention (+85°C)
- Selectable data input and output bit width 8/16/32
- Page storage: 256-Byte
- 3μA bypass current
- Page write time: 8.2ms
1.2 User Flash Resources (GW1NR-2/4/9)
- 10,000 write life cycles
- Data bit width: 32
- GW1NR-2 row storage capacity: 96K bits
- GW1NR-4 row capacity: 256K bits
- GW1NR-9 row storage capacity: 608K bits
- Page erasure capability: 2,048 bytes
- Word programming time: ≤16μs
- Page erase time: ≤120ms
1.3 Low power consumption
- 55nm embedded flash memory process
- LV version: Supports 1.2V core voltage
- UV version: Built-in linear voltage regulator unit, support device VCC/ VCCX / VCCO unified power supply
- Support clock dynamic on/off
1.4 Integrated SDRAM/PSRAM/NOR FLASH memory chip
1.5 Hardcore MIPI D-PHY RX (GW1NR-2)
- Support MIPI DSI, RX device interface
- IO Bank6 supports MIPI D-PHY RX
- MIPI transfer rate up to 1.5Gbps
- Supports up to four data channels and one clock channel
1.6 软核MIPI D-PHY RX/TX(GW1NR-2)
- Supports MIPI CSI-2 and DSI, RX and TX device interfaces
- IO Bank0, IO Bank3, IO Bank4, IO Bank5 support MIPI D-PHY TX, transmission rate up to 1.5Gbps
- IO Bank2 supports MIPI D-PHY RX with transfer rates up to 1.2Gbps
1.7 Supports multiple I/O level standards
- LVCMOS33/25/18/15/12；LVTTL33，SSTL33/25/18 I， SSTL33/25/18 II，SSTL15；HSTL18 I，HSTL18 II，HSTL15 I；PCI，LVDS25，RSDS，LVDS25E，BLVDSE MLVDSE，LVPECLE，RSDSE
- Provides input signal de-hysteresis option
- Support 4mA, 8mA, 16mA, 24mA and other driving capabilities
- Provides output signal slew Rate option
- Output signal drive current option available
- Separate Bus Keeper, pull-up/pull-down resistors, and Open Drain output options are available for each I/O
- Supports hot swapping
- GW1NR-9 device BANK0 supports MIPI I/O inputs at MIPI transfer rates up to 1.2Gbps
- GW1NR-9 device BANK2 supports MIPI I/O output at MIPI transfer rates up to 1.2Gbps
- GW1NR-9 devices BANK0 and BANK2 support I3C OpenDrain/PushPull conversion
1.8 High performance DSP module
- High performance digital signal processing capabilities
- Supports 9 x 9, 18 x 18, 36 x 36 bit multiplication and 54 bit accumulator
- Support multiple multiplier cascades
- Support register pipeline and bypass functions
- Pre-add operation to implement filter function
- Support barrel shift registers
1.9 Rich basic logical units
- 4 input LUT (LUT4)
- Double edge trigger
- Supports shift registers and distributed memory
1.10 Supports multiple modes of static RAM
- Supports dual-port, single-port, and pseudo-dual-port modes
- Supports byte write enablement
1.11 Flexible PLL Resources
- Realize clock multiplier, divide and phase shift
- Global clock network resources
1.12 Built-in Flash programming
- Instantaneous start-
- Supports safe bit operation
- Support AUTO BOOT and DUAL BOOT programming modes
1.13 Programming Configuration Mode
- Support JTAG configuration mode
- Version B device supports JTAG transparent transmission
- Supports up to 7 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT, I2C Slave
2. Product information and package information list
The numbers in parentheses in Table 2-3 represent the logarithm of TLVDS