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Domestic FPGA of Gaoyun - Little Bee Family - GW1N series

author:Deep and shallow FPGA

GW1N series FPGA products are the first generation of Gaoyun Semiconductor LittleBee ®® family, with rich logic resources, support for a variety of I/O level standards, embedded block static RAM, digital signal processing module, phase-locked loop resources, embedded Flash resources (can be understood as CPLD, power failure does not lose), with low power consumption, instantaneous start, low cost, high security, small product size, rich packaging types, easy to use and flexible and so on. The FPGA hardware development environment is completely independent research and development, which can complete one-stop work such as FPGA synthesis, layout, routing, data streaming files and downloads.

1. Characteristic description

1.1 User flash resources (GW1N-1 and GW1N-1S)

- 100,000 write life cycles

- More than 10 years of data retention (+85°C)

- Selectable data input and output bit width 8/16/32

- Page storage: 256-Byte

- 3μA bypass current

- Page write time: 8.2ms

1.2 User Flash Resources (GW1N-1P5/2/4/9)

- 10,000 write life cycles

- Data bit width: 32

- GW1N-1P5/2 row storage capacity: 96K bits

- GW1N-4 row storage capacity: 256K bits

- GW1N-9 row storage capacity: 608K bits

- Page erasure capability: 2,048 bytes

- Word programming time: ≤16μs

- Page erase time: ≤120ms

1.3 Low power consumption

- 55nm embedded flash memory process

- LV version: supports 1.2V core voltage (GW1N-1S only supports LV version)

- UV version: Support device VCC/VCCO/VCCx unified power supply

- Support clock dynamic on/off

1.4 Hardcore MIPI D-PHY RX (GW1N-2)

- Supports MIPI DSI and MIPI CSI-2 RX device interfaces

- MIPI D-PHY RX is supported in the CS42, QN48H, MG132H packages in IO Bank6

- MIPI transmission rates up to 2Gbps per channel

- Supports up to four data channels and one clock channel

1.5 Multifunctional high-speed FPGA IO supports MIPI D-PHY RX/TX (GW1N-2)

- Supports MIPI CSI-2 and MIPI DSI, RX and TX device interfaces with transmission rates up to 1.5Gbps per channel

- IO Bank0, IO Bank3, IO Bank4, IO Bank5 support MIPI D-PHY TX (support dynamic ODT)

- IO Bank2 supports MIPI D-PHY RX (supports dynamic ODT)

1.6 Supports multiple I/O level standards

- LVCMOS33/25/18/15/12;LVTTL33,SSTL33/25/18 I, SSTL33/25/18 II,SSTL15;HSTL18 I,HSTL18 II,HSTL15 I;PCI,LVDS25,RSDS,LVDS25E,BLVDSE,MLVDSE,LVPECLE,RSDSE

- Provides input signal de-hysteresis option

- Support 4mA, 8mA, 16mA, 24mA and other driving capabilities

- Provides output signal slew Rate option

- Output signal drive current option available

- Separate Bus Keeper, pull-up/pull-down resistors, and Open Drain output options are available for each I/O

- Supports hot swapping

- The BANK0/BANK1 of the GW1N-1S device supports MIPI I/O inputs at MIPI transfer rates up to 1.2Gbps

- The top layer of GW1N-9 devices supports MIPI I/O inputs at MIPI transfer rates up to 1.2Gbps

- The GW1N-9 device Bottom layer supports MIPI I/O outputs at MIPI transfer rates up to 1.2Gbps

- GW1N-9 device Top layer and Bottom layer I/O support I3C

1.7 High performance DSP module

- High performance digital signal processing capabilities

- Supports 9 x 9, 18 x 18, 36 x 36 bit multiplication and 54 bit accumulator

- Support multiple multiplier cascades

- Support register pipeline and bypass functions

- Pre-add operation to implement filter function

- Support barrel shift registers

1.8 Rich basic logical units

- 4 input LUT (LUT4)

- Double edge trigger

- Supports shift registers and distributed memory

1.9 Supports multiple modes of static RAM

- Supports dual-port, single-port, and pseudo-dual-port modes

- Supports byte write enablement

1.10 Flexible PLL resources

- Realize clock multiplier, divide and phase shift

- Global clock network resources

1.11 Built-in Flash programming

- Instantaneous start-

- Supports safe bit operation

- Support AUTO BOOT and DUAL BOOT programming modes

1.12 Programming Configuration Mode

- Support JTAG configuration mode

- B version/C version device supports JTAG transparent transmission

- Supports up to 7 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT, I2C Slave

2. Product information and package information list

Domestic FPGA of Gaoyun - Little Bee Family - GW1N series
Domestic FPGA of Gaoyun - Little Bee Family - GW1N series
Domestic FPGA of Gaoyun - Little Bee Family - GW1N series

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