GW1NZ is an ultra-low-power CPLD of the Little Bee family, which is mostly used in low-power products and simple IO control. Similarly, the FPGA hardware development environment is completely independent research and development, which can complete one-stop work such as FPGA synthesis, layout, routing, data streaming files and downloads.
1. Characteristic description
1.1 Zero power consumption
- 55nm embedded flash memory process
- LV version: Supports 1.2V core voltage
- ZV version: Supports 0.9V core voltage
- Support clock dynamic on/off
- Support dynamic on/off user flash
1.2 Power management module (GW1NZ-1)
- SPMI: System power management interface
- The internal VCC and VCCM of the device are independent
1.3 User Flash Resources (GW1NZ-1)
- Support dynamic on or off
- 64K bits
- Data bit width: 32
- 10,000 write life cycles
- More than 10 years of data retention (+85°C)
- Support page erasure: 2048 bytes per page
- Read time: max 25ns
- Current
- 读操作:2.19mA/25ns (VCC) & 0.5mA/25ns (VCCX) (Max)
- Write/Erase Operation: 12/12mA (Max)
- Quick page erase/write operations
- Clock frequency: 40MHz
- Word and write operation time: ≤16μs
- Page erase time: ≤120ms
1.4 Supports multiple I/O level standards
- GW1NZ-1：LVCMOS33/25/18/15/12；LVTTL33， PCI， LVDS25E，BLVDSE，MLVDSE，LVPECLE，RSDSE
- Provides input signal de-hysteresis option
- Support 4mA, 8mA, 16mA, 24mA and other driving capabilities
- Provides output signal slew Rate option
- Output signal drive current option available
- Separate Bus Keeper, pull-up/pull-down resistors, and Open Drain output options are available for each I/O
- Supports hot swapping
- I3C hardcore, support SDR mode
- Only differential outputs are supported, differential inputs are not supported
1.5 Rich basic logical units
- 4 input LUT (LUT4)
- Double edge trigger
- Supports shift registers
- Support for distributed storage
1.6 Supports multiple modes of static RAM
- Supports dual-port, single-port, and pseudo-dual-port modes
- Supports byte write enablement
1.7 Flexible PLL Resources
- Realize clock multiplier, divide and phase shift
- Global clock network resources
1.8 Built-in Flash programming
- Instantaneous start-
- Supports safe bit operation
- Support AUTO BOOT and DUAL BOOT programming modes
1.9 Programming Configuration Mode
- Support JTAG configuration mode
- Supports up to 6 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT
2. Product information and package information list
