Many readers should have heard of ground bombing, but there should be very few problems with ground bombing. This case is an example of a DCDC power supply chip.
1. Problem Description
As shown in Figure 1 below, one of the power supply of the product is a 12V to 3.3V circuit, after the product is shipped about 50K, about 1% of the product can not be started, after decoupling and positioning, the problem is the power chip in the figure below.
Figure 1 12V to 3.3V circuit
2. Cause analysis
After the final analysis, the problem was finally located in relation to the layout and routing of the PCB, which involved an important technology that is easily overlooked: ground bombing.
As shown in the figure below, the left figure is the schematic block diagram inside the chip, and the right figure is the layout diagram in the actual PCB.
(1) When the high-end switch is closed and the low-end switch is disconnected, the path of the current is shown by the red arrow;
(2) When the high-end switch is disconnected and the low-end switch is closed, the path of the current is shown by the blue arrow.
Figure 2 High-low switch inside the chip (left) and actual operation (right)
According to the electromagnetic induction theorem: e=-dФ/dt=-d(Li)/dt=-Ldi/dt, the final embodiment will generate an induced electromotive force between the low-side switch and the Cvin due to the large variation of the loop area between the red and blue loops.
According to the manufacturer's internal manual, the power chip can enter the test mode if it meets the following two conditions, and in the test mode, the power chip does not work and the power supply has no output.
（1）pin5 引脚FB 电压大于3V；
（2）pin6引脚COMP电压小于-0.5V；
The schematic diagram of the PCB we actually designed is shown in the figure below, loop 1 is composed of Cvin, high-side switch, L, Cbuck, and load, loop 2 is composed of Cbuck, load, and loop 3 is composed of low-side switch, L, and load. Among them, the loop area change A is the largest, and the current abrupt change is the most rapid, and the measured pin 6 COMP can reach up to -0.6V. If the interference of the FB pin coupling reaches 3V, the chip can enter test mode, resulting in no output.
Fig.3. Poor layout results in 3 loops
Fig.4. Poor layout produces 3 loops
3. Solution
The main reason for the problem is that the loop area in the two switching states is not the same, which causes the induced electromotive force to change too much, resulting in confusion in the logic inside the chip. The measures after the relayout are as follows:
(1) The input capacitor and the high and low end switches should be on the same horizontal line as far as possible;
(2) Bring the output capacitor and load as close as possible to the power end to eliminate the change caused by loop 2 in the figure above. At the same time, it can cope with the burst current of the electrical equipment, and most of the burst current is powered by the output capacitor, rather than converted by the power supply chip.
(3) Change in loop area after relayout = length of change X plate thickness. The thickness of the plate is 2mm, and the area change is basically negligible.
Figure 5 Optimized layout, the loop change is basically negligible
4. Summary
For DCDC power chips, manufacturers will not disclose their internal specific logic circuits, but one thing is certain, if the loop area changes caused by the two different states of high and low switches, if not handled well, the resulting ground bullet will affect the internal logic, making it enter an uncertain working state.
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