"Moore's Law is Dead" adds new evidence: the cost of chip manufacturing stopped falling 10 years ago

IT Home reported on February 3 that Nvidia CEO Jensen Huang has said in public many times in recent years that "Moore's Law is dead". While Intel and AMD executives disagreed, a recent Google report reaffirmed Huang's view.

Moore's Law, the experience of Gordon Moore, one of Intel's founders, is that the number of transistors that can fit on an integrated circuit doubles approximately every 18 to 24 months. In other words, the performance of the processor doubles roughly every two years, while the price drops to half of what it used to be.

The cost of 100 million gate transistors has stagnated since 28nm in 2014 and has not decreased

Zvi Or-Bach, CEO of MonolithIC 3D, a 3D semiconductor integration company, submitted an analysis back in 2014 showing that the cost per transistor had stopped declining at 28 nanometers.

Google's Milind Shah validated this claim in a short course (SC1.6) at IEDM 2023. He pointed out that since TSMC mass-produced 28nm planar process technology in 2012, the cost per transistor of 100 million gates has actually increased and has not become cheaper.

The graph above shows that the cost of a 100 million gate transistor has not decreased

According to Google's findings, "The increase in transistor cost (0.7x) has stagnated at 28nm and remained flat across generations. ”

There have been long-standing concerns about the diminishing return on the cost per transistor of new nodes. As 7nm, 5nm, and 3nm continue to evolve, chip fabrication process technologies require more sophisticated fab tooling that can cost hundreds of millions of dollars ($200 million for an ASML Twinscan NXE lithography machine) and bring the cost of leading-edge fabs to $20 billion to $30 billion.

However, while chip manufacturing has become more complex and expensive over the past few years, we should look at the problem from a bigger perspective.

In fact, according to a chart presented by Google's Milind Shah at the industry trade show IEDM, the cost of 100 million transistors at 28nm is actually flat and even increasing.

What drives the process?

Why is the industry still pushing transistors to shrink in the incredible 1nm node despite stagnant cost reduction? ™ This chart illustrates this by Bill Dally, chief scientist at NVIDIA®.

Picture: Bill Dally, Berkeley EECS, November 30, 2022

This, in turn, is driving the trend of leading computing devices such as CPUs and GPUs meeting or exceeding particle sizes. The pursuit of smaller nodes allows the components on the chip to be more tightly integrated, further improving performance and efficiency.

The graph below shows the die size trend:

Source: AMD

Unfortunately, the manufacturing processes for logic and memory (DRAM, NAND) are very different. As a result, they are produced on different wafers and cannot be integrated by scaling. To make matters worse, SRAM bit cell scaling stopped at the 5nm node.

Source: WikiChip

Both AMD and TSMC seem to be aware of these trends and have adapted their Hybrid Bonding technology over the past few years to further improve computing performance.

Source: Dr. Lisa Su

Source: TSMC

芯粒（Chiplet）方案受追捧

Chiplet refers to a pre-manufactured, functional, composable and integrated die.

In order to optimize cost and performance, it is more attractive for manufacturers to break down certain designs, i.e., cut them into chiplets, rather than using leading-edge nodes to produce monolithic designs made of monolithic silicon.

Client realms

In the world of client-side computing, the most typical examples of decomposition design are AMD's Ryzen desktop CPUs and Intel's Meteor Lake laptop CPUs, which are manufactured using different processes from different factories.

Data center field

In the data center space, AMD's EPYC data center CPUs are also a success story. Multibillion-dollar companies like AMD and Intel can certainly carefully evaluate their designs and then build products with the best technology at their disposal.

For smaller manufacturers, things may not be so simple.

Multi-core design

First, multi-chiplet designs tend to be more power-hungry than monolithic designs, making them not the best choice for mobile devices.

Multi-chiplet design is a daunting engineering task, and while companies like MonolithIC 3D offer multi-chip integration services (ultimately using advanced packaging technologies such as Intel's Foveros or TSMC's CoWoS), the cost of the service is not cheap.

Third, advanced packaging technology is expensive, and even if some manufacturers are willing to pay for it, TSMC's CoWoS packaging capacity is tight, and it is clear that there is no spare capacity to meet its requirements.

A reference link to this article is attached