In recent years, with people's demand for more advanced performance, advanced processes have become the main battlefield of the "arms race" of major chip manufacturers. It is reported that TSMC's long-delayed 3nm process has made a major breakthrough in the near future, and TSMC may take the lead in completing the mass production of the second version of the 3nm process within this year and name it "N3B".
Intel, which has been pushing the foundry business since Kissinger became CEO, also recently announced that its "Amy-class" 18A process chip will land in advance in 2024.
While chip manufacturers are moving towards more advanced process technology, the yield of manufacturing has become a heart disease for manufacturers. Samsung, which once won Qualcomm's new SoC Snapdragon 8G1 order in 2021, was exposed to a chip yield fraud scandal in the trial production stage at the end of February this year, and the chip yield of some processes below 5nm was even only about 35%.
Qualcomm overturned, Samsung "picked up the pot"
In recent years, Qualcomm has been stuck in the mobile phone SoC business, on the one hand, because the power consumption of the Snapdragon 888 and Snapdragon 8Gen1 chips with a super-large core architecture has "exploded", and the high heat generation has led to a poor user experience.
On the other hand, the cost increases due to the low yield of the product. According to foreign media estimates, the cost of a Snapdragon 888 chip has exceeded $100, while the Snapdragon 8gGen1 costs even higher. The previous Snapdragon 865, which used the 7nm process, cost only $81.
After the scandal broke, Samsung's electronics management department opened an inspection of the DS department on whether the 5nm chip process was true. Compared with the loss of reputation, what makes Samsung "flesh pain" more is the loss of Qualcomm, a big customer.
According to reports, because Samsung Electronics' foundry yield is too low, Qualcomm has decided to transfer the follow-up order of Snapdragon 8Gen1 to TSMC. After that, the foundry business of the new generation of SoC of the 3nm process was handed over to TSMC.
In fact, yield is almost as important to chipmakers as advanced processes. Previously, Todd Edlund, executive vice president and chief operating officer of semiconductor materials manufacturer Entres,Edlund, said in an interview with the media that for 3D NAND fabs, a yield increase of 1% may mean a net profit of $110 million per year; for cutting-edge logic fabs, a 1% yield improvement means a net profit of $150 million.
Today, when Moore's Law is about to be "squeezed dry", the yield of advanced processes is becoming more and more important for chip manufacturers.
Missing vias and random defects: the big trouble with UV
AsML's lithography machines in the Netherlands are an integral part of the manufacturing process of advanced process chips. The mainstream lithography machine technology is divided into DUV and EUV, and only EUV technology can meet the process process below 10nm.
In the process of using EUV lithography machines for wafer etching, random defects may occur, and handling random defects has become a core challenge for manufacturers to improve the yield of advanced processes.
In general, random defects are divided into four categories: line edges and line widths are coarse; CD uniformity errors; overlay errors, and edge shorts or open circuits.
"All of these factors affect the performance, yield and reliability of a device," says Fractilia's Mack.
In defect inspection, optical inspection tools often work with scanning electron microscopy (SEM) to check for possible defects online and classify them. However, the SEM imaging results include both the actual roughness and the roughness due to SEM noise. Traditional image processing filters show average roughness instead of actual roughness.
Mack explains: "For example, a roughness of 4.3 nm may be measured on a wafer, but the metered noise needs to be subtracted to get an actual roughness of 1.3 nm. ”
Fractilia developed detection tools that operate in the frequency domain, using power spectral density to view roughness. With this tool, inspectors can reverse model a wafer model with measured roughness and then analyze it to find each random defect. And the tool also provides engineers with a way to optimize SEM usage, matching tools from different vendors.
On advanced logic chips, accurately locating missing vias or contacts from millions to billions of vias is also a major challenge for yield engineers. In recent years, suppliers of optical inspection tools have significantly updated their tools and software to detect more and more smaller defects.
And with the addition of artificial intelligence to the software, these defects can be better identified.
The most troublesome thing about the defects that can occur in such a complex circuit is that engineers can't determine which areas need attention. At present, there are two ways to identify key areas: the first is to mark the key areas as the previous high-frequency defects by absorbing historical experience. The second method is to find possible weak points from the IC design file, and the software will then take all the areas and automatically generate the focus areas.
For example, engineers at KLA and IBM Reserch recently developed a full array-based binning technology. This technology correlates defects with wafer positions through defect detection. With this technique, engineers found through-holes that had not been marked by previous tools and found problems with the RIE step by tracing specific areas on the wafer.
In this study, engineers at IBM and KLA collaborated to develop a method for capturing missing vias in BEOL logic devices. Engineers used KLA's detection method to define areas of concern around each through hole on the RIE's through-hole chain pattern to improve the sensitivity to the capture of lost through-hole defects.
These areas of concern are then examined using a broadband plasma (BBP) optical tool, and finally the defect is characterized on the SEM review tool. The tool categorizes defects by type.
According to the results, the left side of the path chain is missing at the top, but the missing path on the right side is related to the bottom side. The team therefore suspected that the missing through-hole defect was caused by a blockage due to a misalignment of the previous through-hole etching pattern.
However, traditional inspection methods did not find this defect at the bottom, which means that the strategy can more effectively detect defects that are missing vias in production.
"The inspection results of the BPP system include binning information, which provides process engineers with more actionable data so they can make the best decisions." Kurada concludes.
AFM may become a savior
Although the yield of chip manufacturing has been better controlled in the past with the cooperation of optical inspection system and SEM, in the context of advanced chip process process is getting closer and closer to the limit of Moore's Law, more advanced technology is needed to meet the requirements of yield control.
Igor Schmidt, Bruker's director of operations, said random defects will become increasingly difficult to classify when the chip process reaches below 20nm. AFM becomes especially important where topology data is required to detect depressions and corrosion after CMP.
Igor Schmidt notes that while AFM (Atomic Force Microscopy) throughput is low, it can still be monitored up to 340 per hour for process control of lithography, etching, or CMP processes.
Atomic Force Microscopy (AFM) review tools can use machine vision coordinates to point wafer chart data obtained from optical systems to locations where defects may occur and image the surrounding area.
The results of the imaging will show the 3D dimensions of the area including height information and viscosity.
Sticky data will be able to better help inspectors classify defects. Just as the surface of the rock pile and chewing gum are uneven, but the actual situation represented is different. In defect detection in chip manufacturing, roughness in different viscous cases may point to different results.
If the defect has a large height difference and a large viscosity, it indicates that organic particles or polymers have fallen on the wafer. However, if the viscosity is small in the case of a large difference in height, it may be silicon particles or fragments that fall on the wafer; if there is a pore but no stickiness, it may indicate a stacking or crystallization defect; if no particles are found but are sticky, it indicates that there is a problem with the machine or oil somewhere.
"So it's a powerful technique for defect classification." Igor Schmidt said. Based on this technology, manufacturers will be able to classify defects in chip manufacturing in more detail and accurately on advanced processes, thereby improving product yields.
Leifeng Network
Reference links: https://semiengineering.com/strategies-for-faster-yield-ramps-on-5nm-chips/