【HDLBits刷題】Edgecapture..

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

對于32bit中的每一個變量，我們需要捕獲輸入信号的上升沿。其中捕獲的意思就是說在寄存器複位之前，輸出一直保持為 ‘1’ 。

每一個輸出bit類似SR觸發器：輸出信号從1變0發生時會保持一個周期。輸出會在時鐘上升沿和reset信号為高時複位。如果上述事件在同一時間發生，reset有更高的優先級。在下圖所示的最後4個周期内，reset信号比set信号早一個周期，是以沒有沖突發生。

Module Declaration

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);      

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] temp;
    wire [31:0] capture;

    //同理，我們先檢測輸入信号的上升沿。
    always @ (posedge clk)
        begin
           temp <= in; 
        end
    //這裡如果采用reg的話會出現時序錯誤。
    assign capture = ~in & temp;

    //檢測到上升沿之後，來确定我們的輸出
    always @ (posedge clk)
        begin
            if(reset)
                out <= 32'b0;
            else
                begin
                    for (int i=0; i<32; i=i+1)
                        begin
                            if(capture[i] == 1'b1)
                                out[i] <= 1'b1;
                        end
                end
        end

endmodule
           

本題就是需要我們在檢測到輸入信号的上升沿後，輸出信号在複位之前保持為'1'。