【HDLBits刷题】Edgecapture..

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

对于32bit中的每一个变量，我们需要捕获输入信号的上升沿。其中捕获的意思就是说在寄存器复位之前，输出一直保持为 ‘1’ 。

每一个输出bit类似SR触发器：输出信号从1变0发生时会保持一个周期。输出会在时钟上升沿和reset信号为高时复位。如果上述事件在同一时间发生，reset有更高的优先级。在下图所示的最后4个周期内，reset信号比set信号早一个周期，所以没有冲突发生。

Module Declaration

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);      

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] temp;
    wire [31:0] capture;

    //同理，我们先检测输入信号的上升沿。
    always @ (posedge clk)
        begin
           temp <= in; 
        end
    //这里如果采用reg的话会出现时序错误。
    assign capture = ~in & temp;

    //检测到上升沿之后，来确定我们的输出
    always @ (posedge clk)
        begin
            if(reset)
                out <= 32'b0;
            else
                begin
                    for (int i=0; i<32; i=i+1)
                        begin
                            if(capture[i] == 1'b1)
                                out[i] <= 1'b1;
                        end
                end
        end

endmodule
           

本题就是需要我们在检测到输入信号的上升沿后，输出信号在复位之前保持为'1'。