HDLBits 刷題之我的代碼（全）—（Verilog Language-Procedures）

#1

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
	assign out_assign = a & b;
    always @(*) begin
    	out_alwaysblock = a & b;
    end
endmodule
           

#2

// synthesis verilog_input_version verilog_2001
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
	assign out_assign = a ^ b;
    always @(*) begin
    	out_always_comb = a ^ b;    	
    end
    always @(posedge clk) begin
    	out_always_ff <= a ^ b;    	
    end
endmodule
           

#3

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    assign out_assign = (sel_b1 && sel_b2) ? b : a;
    always @(*) begin
        if((sel_b1 && sel_b2) == 'd1) begin
    		out_always = b; 
        end
        else begin
            out_always = a;	
        end
    end
endmodule
           

#4

// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else 
           shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else
           keep_driving = 0; 
    end

endmodule
           

#5

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
        	'd0:
                out <= data0;
        	'd1:
                out <= data1;
        	'd2:
                out <= data2;
        	'd3:
                out <= data3;
        	'd4:
                out <= data4;
        	'd5:
                out <= data5;
            default:  out <= 'd0;
        endcase
    end

endmodule
           

#6

// synthesis verilog_input_version verilog_2001
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
    always @(*) begin
        case(in)
            4'b0001,4'b0011,4'b0101,4'b1001,4'b0111,4'b1101,4'b1111,4'b1011:
                pos = 'd0;
            4'b0010,4'b0110,4'b1010,4'b1110:
                pos = 'd1;
            4'b0100,4'b1100:
                pos = 'd2;
            4'b1000:
                pos = 'd3;
            default: pos = 'd0;
        endcase
    end
endmodule
           

#7

// synthesis verilog_input_version verilog_2001
module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
    always @(*) begin
        casez(in)
            8'bzzzzzzz1:
                pos = 'd0;
            8'bzzzzzz1z:
                pos = 'd1;
            8'bzzzzz1zz:
                pos = 'd2;
            8'bzzzz1zzz:
                pos = 'd3;
            8'bzzz1zzzz:
                pos = 'd4;
            8'bzz1zzzzz:
                pos = 'd5;
            8'bz1zzzzzz:
                pos = 'd6;
            8'b1zzzzzzz:
                pos = 'd7;
            default: pos = 'd0;
        endcase
    end
endmodule
           

#8

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always @(*) begin
        if(scancode == 16'he06b) begin
            left <= 'd1;
            up <= 'd0;
            right <= 'd0;
            down <= 'd0;           
        end
        else if(scancode == 16'he072) begin
            down <= 'd1;
            left <= 'd0;
            up <= 'd0;
            right <= 'd0;
        end
        else if(scancode == 16'he074) begin
            right <= 'd1;
            down <= 'd0;
            left <= 'd0;
            up <= 'd0;
        end
        else if(scancode == 16'he075) begin
            up <= 'd1;
            right <= 'd0;
            down <= 'd0;
            left <= 'd0;
        end
        else begin
            up <= 'd0;
            right <= 'd0;
            down <= 'd0;
            left <= 'd0;
        end
            
    end
endmodule