基于VHDL語言、狀态機的序列信号發生器的實作

文章目錄

• 一、實驗平台
• 二、實驗描述
• 三、相關代碼
• • 1、主代碼
  • 2、仿真檔案(testbench)
  • 3、分頻相關代碼
• 三、仿真結果

一、實驗平台

1、Basys3開發闆；

2、Vivado2017.4開發環境；

3、VHDL語言。

二、實驗描述

最近在學習時序電路，接觸到狀态機，就利用有限狀态機，寫了一個8位的序列信号發生器（11010010），分為串行輸出和并行輸出。這次隻是仿真，是以沒有進行分頻，不過我會把後面的1HZ分頻代碼貼出來。

三、相關代碼

1、主代碼

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity signal_generate is
    Port (
           clk   : in STD_LOGIC;
           rst   : in STD_LOGIC;
           d     : out STD_LOGIC_VECTOR (7 downto 0);                       --并行輸出
           d_out : out STD_LOGIC                                            --串行輸出
          );
end signal_generate;

architecture Behavioral of signal_generate is
  type states is (s0,s1,s2,s3,s4,s5,s6,s7);
  signal state     : states:=s0;
  signal d1        : std_logic_vector(7 downto 0):="00000000";
  signal temp      : std_logic;
begin
--串并轉換  
  process(clk)
  begin
    if(rst='1')then
      d1<="00000000";
    elsif(clk'event and clk='1')then              
      d1<=d1(6 downto 0)&temp;
    end if;
  end process;
 
----并行輸出序列"11010010"
  process(clk)
    begin
      if(state=s0)then
        d<=d1;                     
      else
        d<=(others=>'0');
      end if;
    end process;
 
--狀态轉移程序 
  process(clk)
  begin
    if(rst='1')then
      state<=s0;
    elsif(clk'event and clk='1')then
      case state is
        when s0 =>
          state<=s1;
        when s1 =>
          state<=s2;
        when s2 =>
          state<=s3;
        when s3 =>
          state<=s4;
        when s4 =>
          state<=s5;
        when s5 =>
          state<=s6;
        when s6 =>
          state<=s7;
        when s7 =>
          state<=s0;
      end case;
    end if;
  end process;
  
--産生序列"11010010"
  process(state)
  begin
    case state is
      when s0 =>
        temp<='1';
      when s1 =>
        temp<='1';
      when s2 =>
        temp<='0';
      when s3 =>
        temp<='1';
      when s4 =>
        temp<='0';
      when s5 =>
        temp<='0';
      when s6 =>
        temp<='1';
      when s7 =>
        temp<='0';    
    end case;
  end process;
    
  d_out<=temp;
end Behavioral;
           

2、仿真檔案(testbench)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity signal_generate_tb is
end signal_generate_tb;

architecture Behavioral of signal_generate_tb is
  component signal_generate
    Port (
           clk   : in STD_LOGIC;
           rst   : in STD_LOGIC;
           d     : out STD_LOGIC_VECTOR (7 downto 0);
           d_out : out STD_LOGIC
           );
  end component;
  
  signal clk   : std_logic:='0';
  signal rst   : std_logic:='0';
  signal d     : std_logic_vector(7 downto 0);
  signal d_out : std_logic;
  constant clk_period : time := 20 ns;
begin
  instant: signal_generate port map
    (clk=>clk,rst=>rst,d=>d,d_out=>d_out);

  clk_gen:process
  begin
    wait for clk_period/2;
    clk<='1';
    wait for clk_period/2;
    clk<='0';
  end process;
  
  rst_gen:process
  begin
    wait for 60 ns;
    rst<='1';
    wait for 10 ns;
    rst<='0';
    wait;           --一直等待
  end process;

end Behavioral;
           

3、分頻相關代碼

--clk=100MHZ,clk_f=1HZ
  count_gen:process(clk)
  begin
    if(clk'event and clk='1')then
      if(count=9)then
        count<=0;     
      else
        count<=count+1;        
      end if;
    end if;
  end process;
  
  clk_f_gen:process(clk)
  begin
    if(clk'event and clk='1')then
      if(count=0)then
        clk_f<=not clk_f;
      else
        clk_f<=clk_f;
      end if;
    end if;  
  end process;
           

三、仿真結果

其中，rst表示複位信号，高電平有效；state表示目前狀态；d_out表示串行輸出；d[7…0]表示并行輸出。

以上就是今天寫的一個關于狀态機的小實驗，如果有問題歡迎大家交流讨論。